115 lines
5.6 KiB
Verilog
115 lines
5.6 KiB
Verilog
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
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// Date : Thu May 1 18:33:54 2025
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// Host : colin-9700k running 64-bit Ubuntu 22.04.5 LTS
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// Command : write_verilog -force -mode synth_stub
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// /home/colin/develop/netfpga_pcie_x1_xdma_bram/IP/xdma_0/xdma_0_stub.v
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// Design : xdma_0
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7k480tffg1156-2L
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "xdma_0_core_top,Vivado 2022.2" *)
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module xdma_0(sys_clk, sys_rst_n, user_lnk_up, pci_exp_txp,
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pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, usr_irq_ack,
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msix_enable, m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
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m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_awid,
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m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awprot, m_axi_awvalid,
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m_axi_awlock, m_axi_awcache, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
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m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
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m_axi_arprot, m_axi_arvalid, m_axi_arlock, m_axi_arcache, m_axi_rready, m_axib_awid,
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m_axib_awaddr, m_axib_awlen, m_axib_awsize, m_axib_awburst, m_axib_awprot, m_axib_awvalid,
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m_axib_awready, m_axib_awlock, m_axib_awcache, m_axib_wdata, m_axib_wstrb, m_axib_wlast,
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m_axib_wvalid, m_axib_wready, m_axib_bid, m_axib_bresp, m_axib_bvalid, m_axib_bready,
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m_axib_arid, m_axib_araddr, m_axib_arlen, m_axib_arsize, m_axib_arburst, m_axib_arprot,
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m_axib_arvalid, m_axib_arready, m_axib_arlock, m_axib_arcache, m_axib_rid, m_axib_rdata,
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m_axib_rresp, m_axib_rlast, m_axib_rvalid, m_axib_rready)
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/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_rst_n,user_lnk_up,pci_exp_txp[0:0],pci_exp_txn[0:0],pci_exp_rxp[0:0],pci_exp_rxn[0:0],axi_aclk,axi_aresetn,usr_irq_req[15:0],usr_irq_ack[15:0],msix_enable,m_axi_awready,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_awid[3:0],m_axi_awaddr[63:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awlock,m_axi_awcache[3:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[63:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arlock,m_axi_arcache[3:0],m_axi_rready,m_axib_awid[3:0],m_axib_awaddr[63:0],m_axib_awlen[7:0],m_axib_awsize[2:0],m_axib_awburst[1:0],m_axib_awprot[2:0],m_axib_awvalid,m_axib_awready,m_axib_awlock,m_axib_awcache[3:0],m_axib_wdata[63:0],m_axib_wstrb[7:0],m_axib_wlast,m_axib_wvalid,m_axib_wready,m_axib_bid[3:0],m_axib_bresp[1:0],m_axib_bvalid,m_axib_bready,m_axib_arid[3:0],m_axib_araddr[63:0],m_axib_arlen[7:0],m_axib_arsize[2:0],m_axib_arburst[1:0],m_axib_arprot[2:0],m_axib_arvalid,m_axib_arready,m_axib_arlock,m_axib_arcache[3:0],m_axib_rid[3:0],m_axib_rdata[63:0],m_axib_rresp[1:0],m_axib_rlast,m_axib_rvalid,m_axib_rready" */;
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input sys_clk;
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input sys_rst_n;
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output user_lnk_up;
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output [0:0]pci_exp_txp;
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output [0:0]pci_exp_txn;
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input [0:0]pci_exp_rxp;
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input [0:0]pci_exp_rxn;
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output axi_aclk;
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output axi_aresetn;
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input [15:0]usr_irq_req;
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output [15:0]usr_irq_ack;
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output msix_enable;
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input m_axi_awready;
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input m_axi_wready;
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input [3:0]m_axi_bid;
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input [1:0]m_axi_bresp;
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input m_axi_bvalid;
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input m_axi_arready;
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input [3:0]m_axi_rid;
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input [63:0]m_axi_rdata;
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input [1:0]m_axi_rresp;
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input m_axi_rlast;
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input m_axi_rvalid;
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output [3:0]m_axi_awid;
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output [63:0]m_axi_awaddr;
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output [7:0]m_axi_awlen;
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output [2:0]m_axi_awsize;
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output [1:0]m_axi_awburst;
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output [2:0]m_axi_awprot;
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output m_axi_awvalid;
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output m_axi_awlock;
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output [3:0]m_axi_awcache;
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output [63:0]m_axi_wdata;
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output [7:0]m_axi_wstrb;
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output m_axi_wlast;
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output m_axi_wvalid;
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output m_axi_bready;
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output [3:0]m_axi_arid;
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output [63:0]m_axi_araddr;
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output [7:0]m_axi_arlen;
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output [2:0]m_axi_arsize;
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output [1:0]m_axi_arburst;
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output [2:0]m_axi_arprot;
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output m_axi_arvalid;
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output m_axi_arlock;
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output [3:0]m_axi_arcache;
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output m_axi_rready;
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output [3:0]m_axib_awid;
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output [63:0]m_axib_awaddr;
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output [7:0]m_axib_awlen;
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output [2:0]m_axib_awsize;
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output [1:0]m_axib_awburst;
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output [2:0]m_axib_awprot;
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output m_axib_awvalid;
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input m_axib_awready;
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output m_axib_awlock;
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output [3:0]m_axib_awcache;
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output [63:0]m_axib_wdata;
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output [7:0]m_axib_wstrb;
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output m_axib_wlast;
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output m_axib_wvalid;
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input m_axib_wready;
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input [3:0]m_axib_bid;
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input [1:0]m_axib_bresp;
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input m_axib_bvalid;
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output m_axib_bready;
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output [3:0]m_axib_arid;
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output [63:0]m_axib_araddr;
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output [7:0]m_axib_arlen;
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output [2:0]m_axib_arsize;
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output [1:0]m_axib_arburst;
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output [2:0]m_axib_arprot;
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output m_axib_arvalid;
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input m_axib_arready;
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output m_axib_arlock;
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output [3:0]m_axib_arcache;
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input [3:0]m_axib_rid;
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input [63:0]m_axib_rdata;
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input [1:0]m_axib_rresp;
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input m_axib_rlast;
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input m_axib_rvalid;
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output m_axib_rready;
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endmodule
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