112 lines
6.1 KiB
VHDL
112 lines
6.1 KiB
VHDL
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
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-- Date : Thu May 1 18:33:54 2025
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-- Host : colin-9700k running 64-bit Ubuntu 22.04.5 LTS
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-- Command : write_vhdl -force -mode synth_stub
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-- /home/colin/develop/netfpga_pcie_x1_xdma_bram/IP/xdma_0/xdma_0_stub.vhdl
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-- Design : xdma_0
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7k480tffg1156-2L
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity xdma_0 is
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Port (
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sys_clk : in STD_LOGIC;
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sys_rst_n : in STD_LOGIC;
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user_lnk_up : out STD_LOGIC;
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pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
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pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
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pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
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pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
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axi_aclk : out STD_LOGIC;
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axi_aresetn : out STD_LOGIC;
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usr_irq_req : in STD_LOGIC_VECTOR ( 15 downto 0 );
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usr_irq_ack : out STD_LOGIC_VECTOR ( 15 downto 0 );
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msix_enable : out STD_LOGIC;
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m_axi_awready : in STD_LOGIC;
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m_axi_wready : in STD_LOGIC;
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m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_bvalid : in STD_LOGIC;
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m_axi_arready : in STD_LOGIC;
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m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_rlast : in STD_LOGIC;
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m_axi_rvalid : in STD_LOGIC;
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m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axi_awvalid : out STD_LOGIC;
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m_axi_awlock : out STD_LOGIC;
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m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axi_wlast : out STD_LOGIC;
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m_axi_wvalid : out STD_LOGIC;
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m_axi_bready : out STD_LOGIC;
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m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axi_arvalid : out STD_LOGIC;
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m_axi_arlock : out STD_LOGIC;
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m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axi_rready : out STD_LOGIC;
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m_axib_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axib_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axib_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axib_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axib_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axib_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axib_awvalid : out STD_LOGIC;
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m_axib_awready : in STD_LOGIC;
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m_axib_awlock : out STD_LOGIC;
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m_axib_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axib_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axib_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axib_wlast : out STD_LOGIC;
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m_axib_wvalid : out STD_LOGIC;
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m_axib_wready : in STD_LOGIC;
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m_axib_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axib_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axib_bvalid : in STD_LOGIC;
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m_axib_bready : out STD_LOGIC;
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m_axib_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axib_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axib_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
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m_axib_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axib_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axib_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
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m_axib_arvalid : out STD_LOGIC;
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m_axib_arready : in STD_LOGIC;
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m_axib_arlock : out STD_LOGIC;
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m_axib_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axib_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
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m_axib_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
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m_axib_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
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m_axib_rlast : in STD_LOGIC;
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m_axib_rvalid : in STD_LOGIC;
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m_axib_rready : out STD_LOGIC
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);
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end xdma_0;
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architecture stub of xdma_0 is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_rst_n,user_lnk_up,pci_exp_txp[0:0],pci_exp_txn[0:0],pci_exp_rxp[0:0],pci_exp_rxn[0:0],axi_aclk,axi_aresetn,usr_irq_req[15:0],usr_irq_ack[15:0],msix_enable,m_axi_awready,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_awid[3:0],m_axi_awaddr[63:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awlock,m_axi_awcache[3:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[63:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arlock,m_axi_arcache[3:0],m_axi_rready,m_axib_awid[3:0],m_axib_awaddr[63:0],m_axib_awlen[7:0],m_axib_awsize[2:0],m_axib_awburst[1:0],m_axib_awprot[2:0],m_axib_awvalid,m_axib_awready,m_axib_awlock,m_axib_awcache[3:0],m_axib_wdata[63:0],m_axib_wstrb[7:0],m_axib_wlast,m_axib_wvalid,m_axib_wready,m_axib_bid[3:0],m_axib_bresp[1:0],m_axib_bvalid,m_axib_bready,m_axib_arid[3:0],m_axib_araddr[63:0],m_axib_arlen[7:0],m_axib_arsize[2:0],m_axib_arburst[1:0],m_axib_arprot[2:0],m_axib_arvalid,m_axib_arready,m_axib_arlock,m_axib_arcache[3:0],m_axib_rid[3:0],m_axib_rdata[63:0],m_axib_rresp[1:0],m_axib_rlast,m_axib_rvalid,m_axib_rready";
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attribute X_CORE_INFO : string;
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attribute X_CORE_INFO of stub : architecture is "xdma_0_core_top,Vivado 2022.2";
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begin
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end;
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