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== Introduction
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Hazard3 is a 3-stage RISC-V processor, providing the following architectural support:
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* `RV32I`: 32-bit base instruction set
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* `M`: integer multiply/divide/modulo
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* `A`: atomic memory operations
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* `C`: compressed instructions
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* `Zba`: address generation
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* `Zbb`: basic bit manipulation
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* `Zbc`: carry-less multiplication
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* `Zbs`: single-bit manipulation
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* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET`
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* The `WFI` instruction
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* `Zicsr`: CSR access
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* The machine-mode (M-mode) privilege state, and standard M-mode CSRs
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* Debug support, fully compliant with version 0.13.2 of the RISC-V external debug specification
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The following are planned for future implementation:
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* Trigger unit for debug mode
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** Likely breakpoints only
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