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Hazard3/example_soc/soc/peri/hazard3_riscv_timer.f

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Add RISC-V timer to example soc, and tweak ULX3S config
2022-10-07 10:11:30 +08:00
file hazard3_riscv_timer.v
file ../../../hdl/debug/cdc/hazard3_sync_1bit.v