Colin 3255e9e952 Pass ECP5 fpga and jlink debug core.		2025-04-02 10:41:27 +08:00
..
peri	Add RISC-V timer to example soc, and tweak ULX3S config	2022-10-07 03:11:36 +01:00
example_soc.v	Pass ECP5 fpga and jlink debug core.	2025-04-02 10:41:27 +08:00
soc.f	Add RISC-V timer to example soc, and tweak ULX3S config	2022-10-07 03:11:36 +01:00