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Hazard3
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a861a110c1
Hazard3
/
test
/
sim
/
riscv-compliance
/
run_32im.sh
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Add 32IM testlist
2021-06-05 19:03:05 +08:00
#!/bin/bash
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 08:35:13 +08:00
set
-e
Update to the latest riscv-arch-test. This uses the new test framework -- scripts are a little janky for now. Note there is one test failure (cebreak-01) -- analysis shows this is due to the reference vector expecting mtval to be set informatively, whereas our implementation (legally) ties it to zero. Non-mtval-related signature for that test is correct so I'm saying this is fine.
2023-03-31 08:39:24 +08:00
make -C riscv-arch-test
RISCV_TARGET
=
hazard3
RISCV_DEVICE
=
I