Luke Wren a861a110c1 Update to the latest riscv-arch-test. This uses the new test ... framework -- scripts are a little janky for now. Note there is one test failure (cebreak-01) -- analysis shows this is due to the reference vector expecting mtval to be set informatively, whereas our implementation (legally) ties it to zero. Non-mtval-related signature for that test is correct so I'm saying this is fine.		2023-03-31 01:39:48 +01:00
..
bitmanip-random	Add Zbkb to bitmanip tests and regenerate vectors	2022-05-21 17:15:46 +01:00
common	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
coremark	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
dhrystone	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
embench	Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)	2022-07-30 17:31:53 +01:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
riscv-compliance	Update to the latest riscv-arch-test. This uses the new test	2023-03-31 01:39:48 +01:00
riscv-tests	Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.	2023-03-26 23:00:18 +01:00
rvcpp	Fix mvsa01/mva01s in rvcpp	2023-03-21 21:54:04 +00:00
rvpy	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
sw_testcases	List Zcb/Zcmp in docs, and rebuild PDF	2023-03-22 03:04:16 +00:00
tb_cxxrtl	Fix rm of build directory in tb_cxxrtl/Makefile	2023-03-30 22:43:48 +01:00