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Rebase riscv-tests against upstream, and pick up new semihosting file io test

This commit is contained in:
Luke Wren 2022-07-04 00:45:20 +01:00
parent e44d2e6f9e
commit 27793b25a1
2 changed files with 6 additions and 5 deletions
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2
test/sim/riscv-tests/riscv-tests

@ -1 +1 @@
Subproject commit 0211e0dacc85d2fa5270e719260f060e21bcc298 Subproject commit b6ac1971d121f25ef32dcc46f033f637a967e55f

9
test/sim/riscv-tests/run-debug-tests.sh
View File

@ -17,6 +17,7 @@ done
--gcc riscv32-unknown-elf-gcc \ --gcc riscv32-unknown-elf-gcc \
targets/luke/hazard3.py \ targets/luke/hazard3.py \
CheckMisa \ CheckMisa \
CrashLoop \
DebugBreakpoint \ DebugBreakpoint \
DebugChangeString \ DebugChangeString \
DebugCompareSections \ DebugCompareSections \
@ -28,12 +29,9 @@ DisconnectTest \
DownloadTest \ DownloadTest \
EbreakTest \ EbreakTest \
InfoTest \ InfoTest \
InterruptTest \
CrashLoop \
InstantChangePc \ InstantChangePc \
InstantHaltTest \ InstantHaltTest \
MemorySampleMixed \ InterruptTest \
MemorySampleSingle \
MemTest16 \ MemTest16 \
MemTest32 \ MemTest32 \
MemTest64 \ MemTest64 \
@ -42,12 +40,15 @@ MemTestBlock0 \
MemTestBlock1 \ MemTestBlock1 \
MemTestBlock2 \ MemTestBlock2 \
MemTestReadInvalid \ MemTestReadInvalid \
MemorySampleMixed \
MemorySampleSingle \
PrivChange \ PrivChange \
PrivRw \ PrivRw \
ProgramSwWatchpoint \ ProgramSwWatchpoint \
Registers \ Registers \
RepeatReadTest \ RepeatReadTest \
Semihosting \ Semihosting \
SemihostingFileio \
SimpleF18Test \ SimpleF18Test \
SimpleNoExistTest \ SimpleNoExistTest \
SimpleS0Test \ SimpleS0Test \