2877350489
Delete unused ecp5_jtag
2025-04-06 17:42:01 +08:00
26f78732fd
Fix final two width lints in JTAG DTM. They now shrink the design by 100 LUTs instead of growing it? A mystery
2024-05-29 15:58:45 +01:00
8b9503c804
lint: clean up a couple of width fixes in JTAG DTM, and add missing
...
default case to DM acmd state machine. Also remove unnecessary clear
of JTAG DR shifter on TAP reset state, which saves a bit of logic. Two
width mismatches are left unfixed in the DTM (the ones with shifts)
because they bizarrely increase area by 100 LUT4s when fixed.
2024-05-27 13:12:18 +01:00
787a7ec372
Fix bad preprocessor conditional in ECP5 JTAG DTM
2022-09-04 23:48:58 +01:00
5d6b5a80b0
Standardise on ifndef YOSYS around default_nettype wire
2022-08-21 13:22:55 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
dfb07822ee
Remove UART DTM
2021-12-02 02:08:16 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
70a44d9681
Small code cleanup
2021-07-24 10:08:27 +01:00
115cb2c50f
Tweaks to example soc configuration
2021-07-23 23:08:23 +01:00
2ae30183aa
Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
2021-07-23 18:32:47 +01:00
8ceae7e9e6
Start hacking on ECP5 JTAG DTM
2021-07-23 00:36:55 +01:00
41477ce479
Extract DTM bus/control logic from the JTAG-related parts
2021-07-22 19:26:25 +01:00
42632e325a
Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
2021-07-12 21:21:16 +01:00
27674be996
Start hacking in a JTAG-DTM
2021-07-12 01:49:32 +01:00
83244c6651
Add Read ID command to UART DTM
2021-07-10 16:14:35 +01:00
Colin
Luke Wren