c6d2b351df
Change clock from 12 to 25.
2025-04-06 19:47:55 +08:00
2877350489
Delete unused ecp5_jtag
2025-04-06 17:42:01 +08:00
7d927cbe73
delete unused file in example_soc/fpga
2025-04-06 17:41:26 +08:00
3255e9e952
Pass ECP5 fpga and jlink debug core.
2025-04-02 10:41:27 +08:00
b188194887
Add led output, refine io plan.
2025-04-01 18:11:04 +08:00
bf0e102e90
Add synth support.
2025-03-31 19:10:52 +08:00
2e649e2c86
Add softuart to soc_cxxrtl test.
2025-03-30 18:36:35 +08:00
464bd40440
Add softuart.
2025-03-30 16:23:29 +08:00
d2942fe094
Add uart software lib.
2025-03-30 00:21:49 +08:00
393499537d
Refine tb main.
2025-03-29 16:22:05 +08:00
aaad0d85a5
Enable aph port off soc, and print prints.
2025-03-27 23:48:10 +08:00
5ec810907e
Refine soc_cxxrtl and pass demo.
2025-03-27 16:02:09 +08:00
616da81d63
Add soc_cxxrtl simulation.
2025-03-26 16:28:09 +08:00
787da131a1
Merge pull request #28 from Wren6991/fix-21
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Coding style change for Verilator compatibility (fixes #21 )
2024-12-09 05:55:00 +00:00
c57e9f4c9b
Coding style change for Verilator compatibility ( fixes #21 )
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The boundary_conditions process in hazard3_frontend needs to be
scheduled at least twice to resolve to the correct values. There are
multiple possible interleavings, which should all result in the same
result. However Verilator schedules the process only once.
Work around this by moving the tie-off of the problematic variable into
the synchronous update process.
2024-12-09 05:35:34 +00:00
8272910121
Merge pull request #23 from Wren6991/fix-dm-abstractauto-regno
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Fix abstract command using wrong register when initiated by abstractauto
2024-10-12 20:03:45 +01:00
cb700f30b1
Fix abstract access GPR command using wrong register number when initiated by abstractauto.
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Fixes #20 . Bug introduced in 78a5cb9
2024-10-12 19:35:13 +01:00
a4412c0b00
Merge pull request #14 from Wren6991/develop
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Promote readme and adoc changes, no functional change
2024-08-09 07:19:01 -07:00
1d0fc21430
Readme.md / doc: clarify "naturally aligned regions", no TOR support
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While NA4 and NAPOT are the only "naturally aligned" addressing modes
in the RISC-V PMP (Privileged) Spec, calling their support out by
name, and clearly stating that the TOR addressing mode is not
supported, can clarify this fact for software / OS developers.
This is a common point of confusion and frustration when porting to
new RISC-V chips and so increased visbility of this limitation in the
documentation and README might help.
2024-08-08 20:44:43 -07:00
b291b46bf1
Update Readme.md
2024-08-08 08:13:27 -07:00
0003e016a0
Update Readme.md
2024-08-08 08:11:54 -07:00
918aaee103
Add note on branches to Contributing.md
2024-08-07 22:53:41 -07:00
7d70dcedec
Add new branch names to Readme.md
2024-08-07 22:51:04 -07:00
5e24d09fda
Fix up embench: use a relative link instead of the old env vars, and fix issues building with the recommended GCC14 configuration
2024-08-07 22:49:00 -07:00
c3913e13ca
Remove unused shell script for old riscv-arch-test
...
(to be picked up again after merging latest riscv-arch-test)
2024-08-07 22:33:15 -07:00
f3cb354b76
Typo in readme
2024-08-07 22:22:05 -07:00
85f53f939e
Wording and typos in Contributing.md
2024-08-07 22:02:04 -07:00
139671613a
Merge down latest riscv-tests. Seems fine, minimal conflicts.
2024-08-07 19:22:02 -07:00
dc21745d16
Hook up hello_multicore to automatically build and use the multicore testbench variant
2024-08-07 19:16:03 -07:00
422c0d32c6
riscv-tests: Update config files for new version of riscv-openocd (currently 5afed58)
2024-08-07 19:02:12 -07:00
42c4ac305b
Fix deprecation warning for tb openocd.cfg, and update example output in Readme.md
2024-08-07 16:44:43 -07:00
1cd5b7fed7
Temporarily disable two riscv-arch-test tests with known issues:
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* jalr-01 uses 'la x0' which is rejected as invalid by recent binutils
* cebreak-01 miscompares due to hardwired mtval (common upstream test issue)
Correct fix is blocked on bringing up the latest riscv-arch-test build
system for hazard3 (seems to have been completely rewritten again)
2024-08-07 16:13:44 -07:00
a9555c8d8c
Add Contributing.md
2024-08-07 14:16:32 -07:00
9c56e669cd
Standardise on a single ISA variant for default test builds, and align this with the lightweight toolchain config in the Readme
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(Automated test builds for multiple ISA variants still yet to be implemented)
2024-08-07 13:34:36 -07:00
ddf7fcacdc
Add note on clang-16 to Readme
2024-08-07 13:19:37 -07:00
aa140fb244
Do a quick pass over all the documentation.
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Fill out port definitions for the AHB5 interfaces.
Snip the appendix of instruction pseudocode as it's strictly redundant
vs the specs. No need to pad this document.
Rearrange the implementation section to put ports before parameters, and
add some brief notes on synthesis.
2024-08-07 13:10:27 -07:00
12d7550be5
Readme: Use non-recursive clone for riscv-gnu-toolchain. Use shallow clone for gcc14. (Save bandwidth and disk space)
2024-08-07 11:40:55 -07:00
fe4781627f
Add port definitions to documentation
2024-08-07 08:16:51 -07:00
0076b408fd
Update readme instructions for Ubuntu 24.04
2024-08-07 07:28:51 -07:00
3c738d0356
Remove redundant masking of meinext_irq field
2024-08-01 08:45:26 +01:00
fbd96363c8
PPA: predecode stage 2 bypass mux controls at end of stage 1
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OR-of-ANDs style mux is used because it maps well on FPGA (particularly
this 3-input mux maps straight onto LUT6) and because this allows the
zeroing of x0 to be implemented directly in the mux
2024-06-06 08:36:55 +01:00
35745117d9
Fix typo in src_only_app.mk
2024-06-06 08:33:55 +01:00
2665e2acc6
Fix case overlap lint in instr_decompress. Now verilator lint clean
2024-06-06 07:18:52 +01:00
e3b3893cdf
Fix partial case overlap lint for shared A/Zbb ALU ops
2024-06-06 06:58:59 +01:00
e34aa5bb45
rvcpp: implement MPRV, and fix up CSR write tracing
2024-06-02 12:46:41 +01:00
877c6aa5ee
Add trace disassembly annotation script for rvcpp, and add runtests support for passing flags to tb, and running post-processing commands on test results.
2024-06-02 11:20:58 +01:00
b026814674
runtests: use argparse for argument parsing, and support passing a different tb executable
2024-06-02 10:36:29 +01:00
a9ba69f4dd
Better default flags for CoreMark
2024-06-02 10:25:07 +01:00
a38981f989
Enable -Wextra for rvcpp
2024-06-02 10:18:40 +01:00
cbc2172930
rvcpp: Add Zcb support. Also fix -Wparentheses as sometimes it does find things
2024-06-02 10:15:57 +01:00
Colin
Luke Wren
Leon Schuermann