Luke Wren
|
63d661af63
|
Start hacking in debug support to the core -- seems to work as well as before adding debug!
|
2021-07-10 18:53:48 +01:00 |
|
Luke Wren
|
6a38fc33a6
|
Allow MHARTID to be configured at instantiation
|
2021-07-07 16:08:08 +01:00 |
|
Luke Wren
|
278dc8b6a2
|
meie0 default to all-zeroes
|
2021-06-04 07:37:02 +01:00 |
Luke Wren
|
af684c4e82
|
Some cleanup; correctly decode 16-bit EBREAK
|
2021-06-03 20:03:43 +01:00 |
|
Luke Wren
|
5f8d217395
|
Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
|
2021-05-31 17:54:12 +01:00 |
|
Luke Wren
|
12851d3742
|
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
|
2021-05-30 19:52:46 +01:00 |
|
Luke Wren
|
cec5dc4e3b
|
Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
|
2021-05-30 19:20:53 +01:00 |
|
Luke Wren
|
565b76672a
|
Make MVENDORID/MARCHID/MIMPID configurable
|
2021-05-30 18:42:43 +01:00 |
|
Luke Wren
|
f23ec3f941
|
Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
|
2021-05-29 18:57:43 +01:00 |
|
Luke Wren
|
65075df0e5
|
More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
|
2021-05-29 18:00:43 +01:00 |
|
Luke Wren
|
1b252d4bda
|
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
|
2021-05-23 11:59:46 +01:00 |
|
Luke Wren
|
844fa8f97f
|
Rename hazard5 -> hazard3
|
2021-05-21 03:46:29 +01:00 |