Luke Wren
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8721bd3deb
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Add RISC-V timer to example soc, and tweak ULX3S config
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2022-10-07 03:11:36 +01:00 |
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Luke Wren
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e68d8a6cd6
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Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
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2022-06-13 01:23:32 +01:00 |
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Luke Wren
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9173bcf585
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Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
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2021-08-21 17:04:15 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |