9 Commits

Author	SHA1	Message	Date
Luke Wren	449348f459	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. ... Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.	2021-12-07 19:24:53 +00:00
Luke Wren	6ef3503ef5	Add A bit to MISA, update docs	2021-12-07 05:10:20 +00:00
Luke Wren	9e7ea4adb6	Fix column width	2021-12-06 17:14:23 +00:00
Luke Wren	df658d86ff	First plausibly working AMOs. Add AMOs to instruction timings list	2021-12-04 23:44:22 +00:00
Luke Wren	a8933c332d	Fix illegal issue of pipelined exclusives on the bus, and document correct timings	2021-12-04 18:23:01 +00:00
Luke Wren	5e17bb805e	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
Luke Wren	0fafae1ab1	Regenerate PDF	2021-11-28 16:27:54 +00:00
Luke Wren	79c29354d2	Update docs with bitmanip instructions	2021-11-28 03:16:45 +00:00
Luke Wren	4053458485	Document some IRQ CSRs, and instruction timings	2021-05-31 15:57:05 +01:00