Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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0b9b706e81
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Safer logic for load/store blocked by preceding WFI
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2021-11-23 22:01:14 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
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Luke Wren
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cfe16caf41
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Remove some old todos
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2021-09-05 22:20:40 +01:00 |
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Luke Wren
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e9fccffca0
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Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
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2021-09-05 04:45:38 +01:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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8e3dc62b97
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Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
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2021-07-16 20:43:24 +01:00 |
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Luke Wren
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5aca6be572
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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
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2021-07-16 18:28:30 +01:00 |
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Luke Wren
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307955c810
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Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
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2021-07-13 01:10:55 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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ea5db61582
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Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)
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2021-05-29 22:52:50 +01:00 |
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Luke Wren
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4b9a3c2c78
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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
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2021-05-29 19:32:12 +01:00 |
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Luke Wren
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f23ec3f941
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Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
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2021-05-29 18:57:43 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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5e61c9f9ac
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Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
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2021-05-23 09:12:50 +01:00 |
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Luke Wren
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7a3ce494e4
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Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
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2021-05-23 06:40:44 +01:00 |
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Luke Wren
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dec78a728d
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Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
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2021-05-22 15:35:52 +01:00 |
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Luke Wren
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08e986912c
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Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
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2021-05-22 11:18:56 +01:00 |
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Luke Wren
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6692c1f26d
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Fix premature taking of branches with RAW data dependencies on the previous instruction
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2021-05-22 10:18:47 +01:00 |
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Luke Wren
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692abbad8b
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Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
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2021-05-22 07:55:13 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |