9e11c0e5a8
Fix tdata1.dmode being writable from M-mode
2022-08-23 00:08:17 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
49c2edeff8
Avoid reserved keyword
2022-08-22 10:26:20 +01:00
53902a901b
Fix bad rdata width for tdata1 (which also caused the trigger type to appear as legacy SiFive, oops)
2022-08-22 09:47:19 +01:00
f9dafa3867
Update readme
2022-08-22 09:25:37 +01:00
b90d12efed
CSRs: avoid use of wdata_update in rdata for meicontext, which the SMT2 backend sees as a loop.
...
There is no functional loop here since this is an acyclic path between different bits of the rdata vector, but it makes sense that this would confuse tools that don't bitblast all the vectors.
2022-08-22 09:18:57 +01:00
ba775563d5
Fix suspicious gating of jump request
2022-08-22 09:10:12 +01:00
6e2076268c
Update CSR readability/writability tests for new CSRs
2022-08-22 08:50:57 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
5d6b5a80b0
Standardise on ifndef YOSYS around default_nettype wire
2022-08-21 13:22:55 +01:00
4c098d76a7
Fix some whitespace issues, and avoid redefinition of RVOPC macros
2022-08-21 13:09:28 +01:00
b994674c5a
Cleanup to avoid negative array index (legal but causes whinging)
2022-08-20 18:13:45 +01:00
3b7cd9bc96
Cleanup some unused signals
2022-08-20 16:44:39 +01:00
96e55a5446
Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation
2022-08-20 16:22:04 +01:00
d299a3ca4e
More width tweaks
2022-08-20 16:11:58 +01:00
bc274867c0
More width mismatch fixes
2022-08-20 15:27:14 +01:00
dbe9a7824a
Cleanup of some width mismatches in instruction decompress
2022-08-20 14:58:41 +01:00
276830ecb6
Fix missing default assignment of i_m in PMP decode
2022-08-16 09:23:42 +01:00
65daa739c4
.gitignore
2022-08-16 09:21:14 +01:00
be05dc32d4
Oops, typo in update of new pmpcfg_m field
2022-08-11 20:46:32 +01:00
8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
f47f603595
Doc typos
2022-08-09 00:05:51 +01:00
cd69fcdbbc
Docs: Add date to title page, and rebuild PDF with recent CSR changes
2022-08-08 23:57:20 +01:00
259a402e28
Describe new pmpcfgm0 register
2022-08-08 23:15:28 +01:00
5819f8eb7e
Remove wrong/useless mxr logic in PMP
2022-08-08 18:45:37 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
92ebbbe95f
Add pmpcfgm0 register: make regions M-mode without locking them
2022-08-08 18:34:55 +01:00
65e3d1c48b
Fix bad IRQ_IMPL_MASK indexing in meipra write
2022-08-08 18:15:38 +01:00
457b5e5f1a
Fix some doc sections which assumed only M-mode was supported
2022-08-08 17:35:39 +01:00
ef927d0d23
Dumb typo
2022-08-08 10:26:36 +01:00
026b529bc5
Fix asm example in docs to set meicontext.clearts when saving
2022-08-07 23:17:39 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
69917ccbbe
Docs: Tweak meicontext with thoughts that came up whilst implementing it
2022-08-07 20:31:14 +01:00
cc12b586ca
Fix implicit net in cpu_1port, this yosys bug is a pain in the ass
2022-08-07 20:30:26 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
054c4a6a9c
Fix reversed pseudocode for ctz/clz
2022-08-02 21:21:44 +01:00
adf81abfdc
Oops, description of shxadd had operands swapped
2022-07-31 17:45:14 +01:00
e76b82e447
More thoughts about interrupts, starting to look plausible
2022-07-31 16:16:16 +01:00
106c4c3d28
Update docs CSR section to reflect addition of U-mode, PMP etc.
2022-07-30 21:19:30 +01:00
797bff81ab
DM: fix any/allnonexistent going low when hasel is set. The hart array mask is in addition to the hart selected by hartsel.
2022-07-30 19:55:22 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
0567c2c9fe
Two minor DM bugs:
...
- Writes to dmcontrol.resumereq should be ignored if dmcontrol.haltreq is also set
- aarsize and regno should be ignored when command.transfer is not set
2022-07-30 17:22:46 +01:00
c73c09a48a
More thinking about interrupt priorities
2022-07-30 15:42:26 +01:00
7946432d7a
Speculatively update docs with new interrupt array/priority stuff, and sleep register
2022-07-28 01:18:13 +01:00
add19506a5
Oops, bad if block nesting in PMP
2022-07-25 13:09:03 +01:00
Luke Wren