Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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4b9a3c2c78
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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
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2021-05-29 19:32:12 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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5e61c9f9ac
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Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
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2021-05-23 09:12:50 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |
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Luke Wren
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7a3ce494e4
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Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
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2021-05-23 06:40:44 +01:00 |
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Luke Wren
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dec78a728d
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Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
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2021-05-22 15:35:52 +01:00 |
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Luke Wren
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692abbad8b
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Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
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2021-05-22 07:55:13 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |