Luke Wren
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9787c604ad
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Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
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2022-07-30 17:31:53 +01:00 |
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Luke Wren
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ee7d8e1947
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Bump embench for script fixes/improvements
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2022-07-07 18:29:37 +01:00 |
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Luke Wren
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91be98f2da
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Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
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2022-07-06 23:53:11 +01:00 |
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Luke Wren
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933f2cd65c
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Fix remaining fallout from tb args change
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2021-12-11 09:53:39 +00:00 |
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Luke Wren
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52ba930638
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Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
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2021-12-04 01:17:57 +00:00 |
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Luke Wren
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fad64bb6c9
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Bump embench test submodule
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2021-11-29 18:51:10 +00:00 |
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Luke Wren
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35c5e213c7
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Bump embench for working benchmarks (except md5)
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2021-11-29 00:59:14 +00:00 |
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Luke Wren
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47ce2cc8ec
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Add embench submodule, with configs for hazard3
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2021-11-28 00:01:18 +00:00 |