4 Commits

Author	SHA1	Message	Date
Luke Wren	a988adfec8	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00
Luke Wren	58c20a39d0	First pass at implementing bitmanip. Breaks CXXRTL. Ooop	2021-11-25 23:30:35 +00:00
Luke Wren	1b252d4bda	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
Luke Wren	844fa8f97f	Rename hazard5 -> hazard3	2021-05-21 03:46:29 +01:00