10 Commits

Author	SHA1	Message	Date
Luke Wren	799f4f2c26	Fix verilator lint width issues in triggers, PMP, DM. ... There was one genuine issue introduced by PPA changes in 78a5cb98e which affected instruction injection on multiple harts from the DM (indicating SMP debug testing needs to be part of regular automated regressions, instead of semi-manual...). The rest are cosmetic.	2024-05-29 15:32:45 +01:00
Luke Wren	43130a16e4	Fix readback of tdata2 and tinfo CSRs ... (Found due to latest riscv-openocd failing to enumerate triggers, as it now scans tinfo before going for tdata1/mcontrol)	2023-03-23 23:33:39 +00:00
Luke Wren	0915cc2834	Doh	2022-09-08 15:11:24 +01:00
Luke Wren	9eb8590858	Add generate to avoid elaborating internals of PMP/triggers with 0 PMP regions or triggers.	2022-09-05 00:36:41 +01:00
Luke Wren	9a60f06c43	Fix trigger enable condition	2022-08-23 01:05:46 +01:00
Luke Wren	9e11c0e5a8	Fix tdata1.dmode being writable from M-mode	2022-08-23 00:08:17 +01:00
Luke Wren	04f138ae0e	Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant	2022-08-23 00:05:30 +01:00
Luke Wren	49c2edeff8	Avoid reserved keyword	2022-08-22 10:26:20 +01:00
Luke Wren	53902a901b	Fix bad rdata width for tdata1 (which also caused the trigger type to appear as legacy SiFive, oops)	2022-08-22 09:47:19 +01:00
Luke Wren	6e3799eed0	First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.	2022-08-22 08:47:03 +01:00