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5 Commits

Author SHA1 Message Date
Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address. 2022-06-13 01:23:32 +01:00
Luke Wren 4946248dc4 RVFI monitor: blank out instructions which experienced an instruction fetch fault. 
(previous monitor logic was ok when fetch faults weren't implemented.
If the blanked instruction has side effects, these will break other test
properties, which we would detect.)
 2022-04-12 13:38:19 +01:00
Luke Wren 8a61fe5243 Fix RVFI monitor assuming rs2 data is equivalent to store data 
(this used to be true, but was re-plumbed when optimising A extension implementation)
 2022-04-12 13:27:53 +01:00
Luke Wren 9e27db0884 Connect or tie off missing ports on RVFI wrapper 2022-04-12 13:27:03 +01:00
Luke Wren 2330b84b73 Use .f for riscv-formal tb dependencies, small reshuffling of directories 2021-05-30 09:44:57 +01:00