Luke Wren
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76172cdade
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Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
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2021-11-28 06:33:35 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
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Luke Wren
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cfe16caf41
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Remove some old todos
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2021-09-05 22:20:40 +01:00 |
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Luke Wren
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e9fccffca0
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Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
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2021-09-05 04:45:38 +01:00 |
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Luke Wren
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65bfca5fdf
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Fix latent bug with asynchronous debug entry during stalled load/store address phase
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2021-09-04 07:49:29 +01:00 |
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Luke Wren
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8263ee3a5d
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Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
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2021-07-24 15:31:33 +01:00 |
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Luke Wren
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155d3ba554
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Tie off 1 or 2 LSBs of DPC depending on IALIGN
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2021-07-23 23:09:03 +01:00 |
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Luke Wren
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279e4b4f29
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Implement mstatush as hardwired-0, as required by priv-1.12
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2021-07-23 21:52:01 +01:00 |
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Luke Wren
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7d24f42da9
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Oops, properly fix platform IRQ mcause numbers
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2021-07-19 09:32:59 +01:00 |
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Luke Wren
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65fb62901e
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Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
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2021-07-19 00:19:56 +01:00 |
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Luke Wren
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70443fa557
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Disable shifting of MIE/MPIE stack when in or entering debug mode
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2021-07-18 21:14:11 +01:00 |
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Luke Wren
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d30fc46f5b
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Fix IRQ mcause not being set correctly when vectoring is disabled
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2021-07-18 20:44:39 +01:00 |
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Luke Wren
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e95b465e26
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Typo in address of mcountinhibit!
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2021-07-17 19:27:01 +01:00 |
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Luke Wren
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8e3dc62b97
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Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
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2021-07-16 20:43:24 +01:00 |
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Luke Wren
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5aca6be572
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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
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2021-07-16 18:28:30 +01:00 |
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Luke Wren
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011008efd1
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Fix detection of exception-like vs IRQ-like halt/trap entries
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2021-07-15 19:41:35 +01:00 |
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Luke Wren
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71ec9fa283
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Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
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2021-07-14 20:39:51 +01:00 |
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Luke Wren
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5cc483898d
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Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
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2021-07-10 21:02:18 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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6a38fc33a6
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Allow MHARTID to be configured at instantiation
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2021-07-07 16:08:08 +01:00 |
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Luke Wren
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278dc8b6a2
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meie0 default to all-zeroes
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2021-06-04 07:37:02 +01:00 |
Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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cec5dc4e3b
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Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
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2021-05-30 19:20:53 +01:00 |
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Luke Wren
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565b76672a
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Make MVENDORID/MARCHID/MIMPID configurable
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2021-05-30 18:42:43 +01:00 |
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Luke Wren
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f23ec3f941
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Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
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2021-05-29 18:57:43 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |