0b18fae32e
Fix swapped MHARTID/MCONFIGPTR values in tb configs
2022-10-08 08:42:50 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
a18c3018e1
Bump riscv-formal to head of hazard3 branch, not sure what happened there
2022-10-07 01:35:10 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
da4097ecd8
Delay pwrup_req->pwrup_ack in tb
2022-08-29 14:55:11 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
a79c857d82
Bump riscv-tests: enable hardware instruction breakpoints in hardware tests
2022-08-27 17:05:02 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
6e2076268c
Update CSR readability/writability tests for new CSRs
2022-08-22 08:50:57 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
ee7d8e1947
Bump embench for script fixes/improvements
2022-07-07 18:29:37 +01:00
91be98f2da
Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
2022-07-06 23:53:11 +01:00
5a39d8b7e7
Track minstret and mcycle separately now that the model is cycle-accurate
2022-07-06 13:50:13 +01:00
5dfe5cb62b
Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
2022-07-06 13:49:51 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
27793b25a1
Rebase riscv-tests against upstream, and pick up new semihosting file io test
2022-07-04 00:45:20 +01:00
e44d2e6f9e
Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
2022-07-03 23:34:12 +01:00
b1225c386c
Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
2022-07-03 17:57:03 +01:00
9e15cd3485
Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
2022-07-03 15:30:33 +01:00
d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
51bc26f8ac
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
2022-07-03 00:25:47 +01:00
a7cb214501
Reduce ROM size in instruction_fetch_match: depth is more useful
2022-06-26 19:59:44 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
...
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
8ef9d77be8
Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
...
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
2022-06-25 13:11:40 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
d31b1708db
Make rvpy cycle-accurate enough to get the correct Dhrystone score
2022-06-09 01:34:37 +01:00
02b303b385
Remove stray old expected output file from sw_testcases dir
2022-06-03 17:20:49 +01:00
e2c9901701
Update readme for runtests
2022-05-30 01:12:16 +01:00
2cfe6aa90e
Add test to check MPRV/MPP behaviour when executing an MRET
2022-05-29 19:51:19 +01:00
f96a0ffb75
Add test for MPRV vs PMP
2022-05-29 19:06:04 +01:00
71eff7649d
Add PMP U-mode read/write permission test
2022-05-29 18:42:44 +01:00
c8afcdbb8f
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
2022-05-29 17:42:15 +01:00
Luke Wren