115 Commits

Author	SHA1	Message	Date
Luke Wren	ce5cc1f150	oops, bounds checking on free-running tb_cxxrtl	2021-07-18 15:20:25 +01:00
Luke Wren	8014239d47	openocd tb: report AHB error response when processor accesses outside of RAM/IO	2021-07-17 19:26:05 +01:00
Luke Wren	ab0b4a04f0	Also support progbuf in abstractauto.	2021-07-17 15:08:00 +01:00
Luke Wren	62822b2e1d	Couple of usability improvements for openocd testbench	2021-07-15 19:42:49 +01:00
Luke Wren	9643a57ba9	Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now	2021-07-14 19:20:27 +01:00
Luke Wren	307955c810	Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference	2021-07-13 01:10:55 +01:00
Luke Wren	42632e325a	Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core	2021-07-12 21:21:16 +01:00
Luke Wren	f7b3097ad6	Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works	2021-07-11 16:20:39 +01:00
Luke Wren	5cc483898d	Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode	2021-07-10 21:02:18 +01:00
Luke Wren	58a6b8b4c8	Add 32IM testlist	2021-06-05 12:03:05 +01:00
Luke Wren	be79a611e1	Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.	2021-06-04 09:19:18 +01:00
Luke Wren	c03bc2efb5	Update init.S for new IRQ functionality	2021-06-04 08:16:54 +01:00
Luke Wren	12851d3742	Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set	2021-05-30 19:52:46 +01:00
Luke Wren	1b252d4bda	Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2	2021-05-23 11:59:46 +01:00
Luke Wren	90acfdcbe8	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00