Luke Wren
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e89ab0d095
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tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
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2023-03-31 02:11:52 +01:00 |
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Luke Wren
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dff278ea05
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Increase DTM idle cycle hint to 8 cycles -- see #6
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2022-10-19 21:11:18 +01:00 |
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Luke Wren
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874cb20910
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Add config headers to tb_cxxrtl instead of using defparams in Makefile
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2022-10-08 08:09:26 +01:00 |
|
Luke Wren
|
da4097ecd8
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Delay pwrup_req->pwrup_ack in tb
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2022-08-29 14:55:11 +01:00 |
|
Luke Wren
|
2ae2463b97
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First stab at adding wake/sleep state machine
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2022-08-28 19:50:04 +01:00 |
|
Luke Wren
|
15cb21ae43
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First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
|
2022-08-07 20:51:12 +01:00 |
|
Luke Wren
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9e15cd3485
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Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
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2022-07-03 15:30:33 +01:00 |
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Luke Wren
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51bc26f8ac
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First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
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2022-07-03 00:25:47 +01:00 |
|
Luke Wren
|
5ab60422ad
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Add minimal multicore launch code
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2021-12-17 01:24:11 +00:00 |
|
Luke Wren
|
207566660d
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tb: handle both ports identically. Preparing for dual core
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2021-12-17 00:04:00 +00:00 |
|
Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |