Luke Wren
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9787c604ad
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Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
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2022-07-30 17:31:53 +01:00 |
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Luke Wren
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91be98f2da
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Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
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2022-07-06 23:53:11 +01:00 |
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Luke Wren
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d9389fb23e
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Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
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2022-06-16 01:42:28 +01:00 |
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Luke Wren
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ef35dc859d
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Add zicsr to march in makefiles
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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c03bc2efb5
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Update init.S for new IRQ functionality
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2021-06-04 08:16:54 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |