example_soc/soc/example_soc.v

@@ -18,7 +18,6 @@ module example_soc #(
 	// System clock + reset
 	input wire               clk,
 	input wire               rst_n,
-	output wire               led_o,
 
 	// JTAG port to RISC-V JTAG-DTM
 	input  wire              tck,
@@ -56,15 +55,6 @@ reg  [31:0]       dmi_prdata;
 wire              dmi_pready;
 wire              dmi_pslverr;
 
-reg  [31:0] cpt_s;
-wire [31:0] cpt_next_s = cpt_s + 1'b1;
-assign led_o = cpt_s[22];
-
-always @(posedge clk) begin
-	if (rst_n) begin
-	  cpt_s <= cpt_next_s;
-	end
-end
 
 // TCK-domain DTM logic can force a hard reset
 wire dmihardreset_req;

test/sim/hellow/main.c

@@ -16,8 +16,8 @@ int main() {
   uart_wait_done();
 
   // tb_puts("Hello world from Hazard3 + CXXRTL!\n");
-  // uint32_t addr = 0x40008000;
+  uint32_t addr = 0x40008000;
-  // uint32_t *point = (uint32_t *)addr;
+  uint32_t *point = (uint32_t *)addr;
-  // *point = 'C';
+  *point = 'C';
   return 123;
 }

test/sim/soc_cxxrtl/Makefile

@@ -34,18 +34,18 @@ synth: $(FILE_LIST) $(wildcard *.vh)
 	yosys -p '$(SYNTH_CMD)'
 
 nextpnr:
-	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --lpf-allow-unconstrained --textcfg $(BUILD_DIR)/soc.cfg --lpf soc.lpf --freq 25  --json $(BUILD_DIR)/soc.json
+	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --lpf-allow-unconstrained --textcfg $(BUILD_DIR)/soc.cfg --lpf soc.lpf --freq 12  --json $(BUILD_DIR)/soc.json
 
 $(BUILD_DIR)/soc.bit: $(BUILD_DIR)/soc.cfg
 	ecppack --svf $(BUILD_DIR)/soc.svf ./$< ./$@
 
 $(BUILD_DIR)/soc.svf : $(BUILD_DIR)/soc.bit
 
-prog: $(BUILD_DIR)/soc.bit
+prog: $(BUILD_DIR)/soc.svf
-	ecpdap program $(BUILD_DIR)/soc.bit
+	ecpdap program $(BUILD_DIR)/soc.svf
 
 flash: $(BUILD_DIR)/soc.bit
-	ecpdap flash write $(BUILD_DIR)/soc.bit
+	ecpdap flash write $(BUILD_DIR)/soc.svf
 
 
 CXXRTL_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(FILE_LIST);
@@ -65,9 +65,6 @@ sim: $(TBEXEC)
 openocd:
 	openocd -f openocd.cfg
 
-jlink:
-	openocd -f openocd-jlink.cfg
-
 gdb:
 	/opt/riscv/bin/riscv32-unknown-elf-gdb -x gdb_init
 

test/sim/soc_cxxrtl/openocd-jlink.cfg

@@ -1,15 +0,0 @@
-
-adapter driver jlink
-transport select jtag
-adapter speed 2000
-
-transport select jtag
-
-set _CHIPNAME hazard3
-jtag newtap $_CHIPNAME cpu -irlen 5
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-gdb_report_data_abort enable
-init
-halt

test/sim/soc_cxxrtl/soc.lpf

@@ -3,18 +3,16 @@ LOCATE COMP "clk" SITE "P3";
 IOBUF PORT "clk" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "clk" 25 MHZ;
 
-LOCATE COMP "led_o" SITE "U16";
-IOBUF PORT "led_o" IO_TYPE=LVCMOS33;
 
+LOCATE COMP "trst_n" SITE "D20";
+IOBUF PORT "trst_n" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "trst_n" 25 MHZ;
 
 LOCATE COMP "rst_n" SITE "B19";
-IOBUF PORT "rst_n" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "rst_n" 25 MHZ;
 
 
-LOCATE COMP "trst_n" SITE "H5";
-IOBUF PORT "trst_n" PULLMODE=UP IO_TYPE=LVCMOS33;
-FREQUENCY PORT "trst_n" 25 MHZ;
 
 LOCATE COMP "tdi" SITE "E1";
 IOBUF PORT "tdi" IO_TYPE=LVCMOS33;
@@ -32,10 +30,9 @@ IOBUF PORT "tms" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "tms" 25 MHZ;
 
 
-LOCATE COMP "uart_rx" SITE "D20";
+LOCATE COMP "uart_rx" SITE "J5";
 IOBUF PORT "uart_rx" IO_TYPE=LVCMOS33;
 FREQUENCY PORT "uart_rx" 25 MHZ;
 
-LOCATE COMP "uart_tx" SITE "F20";
+LOCATE COMP "uart_tx" SITE "U16";
 IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33;
-FREQUENCY PORT "uart_tx" 25 MHZ;