604 lines
18 KiB
Verilog
604 lines
18 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Example file integrating a Hazard3 processor, processor JTAG + debug
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// components, some memory and a UART.
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`default_nettype none
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module example_soc #(
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parameter DTM_TYPE = "JTAG", // Can be "JTAG" or "ECP5"
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parameter SRAM_DEPTH = 1 << 14, // Default 16 kwords -> 64 kB
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parameter CLK_MHZ = 12, // For timer timebase
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`include "hazard3_config.vh"
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) (
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// System clock + reset
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input wire clk,
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input wire rst_n,
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output wire led_o,
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// JTAG port to RISC-V JTAG-DTM
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input wire tck,
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input wire trst_n,
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input wire tms,
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input wire tdi,
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output wire tdo,
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// IO
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output wire uart_tx,
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input wire uart_rx,
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output wire gp_psel,
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output wire gp_penable,
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output wire gp_pwrite,
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output wire [15:0] gp_paddr,
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output wire [31:0] gp_pwdata,
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input wire [31:0] gp_prdata,
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input wire gp_pready,
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input wire gp_pslverr,
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);
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localparam W_ADDR = 32;
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localparam W_DATA = 32;
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// ----------------------------------------------------------------------------
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// Processor debug
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wire dmi_psel;
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wire dmi_penable;
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wire dmi_pwrite;
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wire [8:0] dmi_paddr;
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wire [31:0] dmi_pwdata;
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reg [31:0] dmi_prdata;
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wire dmi_pready;
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wire dmi_pslverr;
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reg [31:0] cpt_s;
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wire [31:0] cpt_next_s = cpt_s + 1'b1;
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assign led_o = cpt_s[22];
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always @(posedge clk) begin
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if (rst_n) begin
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cpt_s <= cpt_next_s;
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end
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end
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// TCK-domain DTM logic can force a hard reset
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wire dmihardreset_req;
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wire assert_dmi_reset = !rst_n || dmihardreset_req;
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wire rst_n_dmi;
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reset_sync dmi_reset_sync_u (
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.clk (clk),
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.rst_n_in (!assert_dmi_reset),
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.rst_n_out (rst_n_dmi)
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);
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generate
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if (DTM_TYPE == "JTAG") begin
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// Standard RISC-V JTAG-DTM connected to external IOs.
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// JTAG-DTM IDCODE should be a JEP106-compliant ID:
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localparam IDCODE = 32'hdeadbeef;
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hazard3_jtag_dtm #(
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.IDCODE (IDCODE)
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) dtm_u (
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.tck (tck),
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.trst_n (trst_n),
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.tms (tms),
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.tdi (tdi),
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.tdo (tdo),
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.dmihardreset_req (dmihardreset_req),
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.clk_dmi (clk),
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.rst_n_dmi (rst_n_dmi),
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.dmi_psel (dmi_psel),
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.dmi_penable (dmi_penable),
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.dmi_pwrite (dmi_pwrite),
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.dmi_paddr (dmi_paddr),
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.dmi_pwdata (dmi_pwdata),
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.dmi_prdata (dmi_prdata),
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.dmi_pready (dmi_pready),
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.dmi_pslverr (dmi_pslverr)
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);
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end else if (DTM_TYPE == "ECP5") begin
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// Attach RISC-V DTM's DTMCS/DMI registers to ECP5 ER1/ER2 registers. This
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// allows the processor to be debugged through the ECP5 chip TAP, using
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// regular upstream OpenOCD.
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// Connects to ECP5 TAP internally by instantiating a JTAGG primitive.
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assign tdo = 1'b0;
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hazard3_ecp5_jtag_dtm dtm_u (
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.dmihardreset_req (dmihardreset_req),
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.clk_dmi (clk),
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.rst_n_dmi (rst_n_dmi),
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.dmi_psel (dmi_psel),
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.dmi_penable (dmi_penable),
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.dmi_pwrite (dmi_pwrite),
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.dmi_paddr (dmi_paddr),
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.dmi_pwdata (dmi_pwdata),
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.dmi_prdata (dmi_prdata),
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.dmi_pready (dmi_pready),
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.dmi_pslverr (dmi_pslverr)
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);
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end
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endgenerate
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localparam N_HARTS = 1;
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localparam XLEN = 32;
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wire sys_reset_req;
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wire sys_reset_done;
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wire [N_HARTS-1:0] hart_reset_req;
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wire [N_HARTS-1:0] hart_reset_done;
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wire [N_HARTS-1:0] hart_req_halt;
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wire [N_HARTS-1:0] hart_req_halt_on_reset;
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wire [N_HARTS-1:0] hart_req_resume;
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wire [N_HARTS-1:0] hart_halted;
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wire [N_HARTS-1:0] hart_running;
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wire [N_HARTS*XLEN-1:0] hart_data0_rdata;
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wire [N_HARTS*XLEN-1:0] hart_data0_wdata;
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wire [N_HARTS-1:0] hart_data0_wen;
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wire [N_HARTS*XLEN-1:0] hart_instr_data;
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wire [N_HARTS-1:0] hart_instr_data_vld;
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wire [N_HARTS-1:0] hart_instr_data_rdy;
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wire [N_HARTS-1:0] hart_instr_caught_exception;
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wire [N_HARTS-1:0] hart_instr_caught_ebreak;
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wire [31:0] sbus_addr;
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wire sbus_write;
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wire [1:0] sbus_size;
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wire sbus_vld;
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wire sbus_rdy;
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wire sbus_err;
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wire [31:0] sbus_wdata;
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wire [31:0] sbus_rdata;
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hazard3_dm #(
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.N_HARTS (N_HARTS),
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.HAVE_SBA (0),
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.NEXT_DM_ADDR (0)
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) dm (
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.clk (clk),
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.rst_n (rst_n),
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.dmi_psel (dmi_psel),
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.dmi_penable (dmi_penable),
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.dmi_pwrite (dmi_pwrite),
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.dmi_paddr (dmi_paddr),
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.dmi_pwdata (dmi_pwdata),
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.dmi_prdata (dmi_prdata),
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.dmi_pready (dmi_pready),
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.dmi_pslverr (dmi_pslverr),
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.sys_reset_req (sys_reset_req),
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.sys_reset_done (sys_reset_done),
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.hart_reset_req (hart_reset_req),
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.hart_reset_done (hart_reset_done),
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.hart_req_halt (hart_req_halt),
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.hart_req_halt_on_reset (hart_req_halt_on_reset),
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.hart_req_resume (hart_req_resume),
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.hart_halted (hart_halted),
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.hart_running (hart_running),
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.hart_data0_rdata (hart_data0_rdata),
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.hart_data0_wdata (hart_data0_wdata),
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.hart_data0_wen (hart_data0_wen),
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.hart_instr_data (hart_instr_data),
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.hart_instr_data_vld (hart_instr_data_vld),
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.hart_instr_data_rdy (hart_instr_data_rdy),
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.hart_instr_caught_exception (hart_instr_caught_exception),
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.hart_instr_caught_ebreak (hart_instr_caught_ebreak),
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.sbus_addr (sbus_addr),
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.sbus_write (sbus_write),
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.sbus_size (sbus_size),
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.sbus_vld (sbus_vld),
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.sbus_rdy (sbus_rdy),
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.sbus_err (sbus_err),
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.sbus_wdata (sbus_wdata),
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.sbus_rdata (sbus_rdata)
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);
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// Generate resynchronised reset for CPU based on upstream system reset and on
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// system/hart reset requests from DM.
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wire assert_cpu_reset = !rst_n || sys_reset_req || hart_reset_req[0];
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wire rst_n_cpu;
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reset_sync cpu_reset_sync (
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.clk (clk),
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.rst_n_in (!assert_cpu_reset),
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.rst_n_out (rst_n_cpu)
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);
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// Still some work to be done on the reset handshake -- this ought to be
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// resynchronised to DM's reset domain here, and the DM should wait for a
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// rising edge after it has asserted the reset pulse, to make sure the tail
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// of the previous "done" is not passed on.
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assign sys_reset_done = rst_n_cpu;
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assign hart_reset_done = rst_n_cpu;
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// ----------------------------------------------------------------------------
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// Processor
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wire [W_ADDR-1:0] proc_haddr;
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wire proc_hwrite;
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wire [1:0] proc_htrans;
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wire [2:0] proc_hsize;
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wire [2:0] proc_hburst;
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wire [3:0] proc_hprot;
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wire proc_hmastlock;
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wire proc_hexcl;
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wire proc_hready;
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wire proc_hresp;
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wire proc_hexokay = 1'b1; // No global monitor
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wire [W_DATA-1:0] proc_hwdata;
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wire [W_DATA-1:0] proc_hrdata;
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wire pwrup_req;
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wire unblock_out;
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wire uart_irq;
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wire timer_irq;
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hazard3_cpu_1port #(
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// These must have the values given here for you to end up with a useful SoC:
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.RESET_VECTOR (32'h0000_0040),
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.MTVEC_INIT (32'h0000_0000),
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.CSR_M_MANDATORY (1),
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.CSR_M_TRAP (1),
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.DEBUG_SUPPORT (1),
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.NUM_IRQS (1),
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.RESET_REGFILE (0),
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// Can be overridden from the defaults in hazard3_config.vh during
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// instantiation of example_soc():
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.EXTENSION_A (EXTENSION_A),
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.EXTENSION_C (EXTENSION_C),
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.EXTENSION_M (EXTENSION_M),
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.EXTENSION_ZBA (EXTENSION_ZBA),
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.EXTENSION_ZBB (EXTENSION_ZBB),
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.EXTENSION_ZBC (EXTENSION_ZBC),
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.EXTENSION_ZBS (EXTENSION_ZBS),
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.EXTENSION_ZBKB (EXTENSION_ZBKB),
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.EXTENSION_ZIFENCEI (EXTENSION_ZIFENCEI),
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.EXTENSION_XH3BEXTM (EXTENSION_XH3BEXTM),
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.EXTENSION_XH3IRQ (EXTENSION_XH3IRQ),
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.EXTENSION_XH3PMPM (EXTENSION_XH3PMPM),
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.EXTENSION_XH3POWER (EXTENSION_XH3POWER),
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.CSR_COUNTER (CSR_COUNTER),
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.U_MODE (U_MODE),
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.PMP_REGIONS (PMP_REGIONS),
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.PMP_GRAIN (PMP_GRAIN),
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.PMP_HARDWIRED (PMP_HARDWIRED),
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.PMP_HARDWIRED_ADDR (PMP_HARDWIRED_ADDR),
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.PMP_HARDWIRED_CFG (PMP_HARDWIRED_CFG),
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.MVENDORID_VAL (MVENDORID_VAL),
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.BREAKPOINT_TRIGGERS (BREAKPOINT_TRIGGERS),
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.IRQ_PRIORITY_BITS (IRQ_PRIORITY_BITS),
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.MIMPID_VAL (MIMPID_VAL),
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.MHARTID_VAL (MHARTID_VAL),
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.REDUCED_BYPASS (REDUCED_BYPASS),
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.MULDIV_UNROLL (MULDIV_UNROLL),
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.MUL_FAST (MUL_FAST),
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.MUL_FASTER (MUL_FASTER),
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.MULH_FAST (MULH_FAST),
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.FAST_BRANCHCMP (FAST_BRANCHCMP),
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.BRANCH_PREDICTOR (BRANCH_PREDICTOR),
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.MTVEC_WMASK (MTVEC_WMASK)
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) cpu (
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.clk (clk),
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.clk_always_on (clk),
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.rst_n (rst_n_cpu),
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.pwrup_req (pwrup_req),
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.pwrup_ack (pwrup_req), // Tied back
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.clk_en (/* unused */),
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.unblock_out (unblock_out),
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.unblock_in (unblock_out), // Tied back
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.haddr (proc_haddr),
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.hwrite (proc_hwrite),
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.htrans (proc_htrans),
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.hsize (proc_hsize),
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.hburst (proc_hburst),
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.hprot (proc_hprot),
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.hmastlock (proc_hmastlock),
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.hexcl (proc_hexcl),
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.hready (proc_hready),
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.hresp (proc_hresp),
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.hexokay (proc_hexokay),
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.hwdata (proc_hwdata),
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.hrdata (proc_hrdata),
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.dbg_req_halt (hart_req_halt),
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.dbg_req_halt_on_reset (hart_req_halt_on_reset),
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.dbg_req_resume (hart_req_resume),
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.dbg_halted (hart_halted),
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.dbg_running (hart_running),
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.dbg_data0_rdata (hart_data0_rdata),
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.dbg_data0_wdata (hart_data0_wdata),
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.dbg_data0_wen (hart_data0_wen),
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.dbg_instr_data (hart_instr_data),
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.dbg_instr_data_vld (hart_instr_data_vld),
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.dbg_instr_data_rdy (hart_instr_data_rdy),
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.dbg_instr_caught_exception (hart_instr_caught_exception),
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.dbg_instr_caught_ebreak (hart_instr_caught_ebreak),
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.dbg_sbus_addr (sbus_addr),
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.dbg_sbus_write (sbus_write),
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.dbg_sbus_size (sbus_size),
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.dbg_sbus_vld (sbus_vld),
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.dbg_sbus_rdy (sbus_rdy),
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.dbg_sbus_err (sbus_err),
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.dbg_sbus_wdata (sbus_wdata),
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.dbg_sbus_rdata (sbus_rdata),
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.irq (uart_irq),
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.soft_irq (1'b0),
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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// Bus fabric
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// - 128 kB SRAM at... 0x0000_0000 Mask: 0xe0000000
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// - System timer at.. 0x4000_0000 Mask: 0xe000c000
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// - UART at.......... 0x4000_4000 Mask: 0xe000c000
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// - GP at.......... 0x4000_8000 Mask: 0xe000c000
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// AHBL layer
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wire sram0_hready_resp;
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wire sram0_hready;
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wire sram0_hresp;
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wire [W_ADDR-1:0] sram0_haddr;
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wire sram0_hwrite;
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wire [1:0] sram0_htrans;
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wire [2:0] sram0_hsize;
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wire [2:0] sram0_hburst;
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wire [3:0] sram0_hprot;
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wire sram0_hmastlock;
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wire [W_DATA-1:0] sram0_hwdata;
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wire [W_DATA-1:0] sram0_hrdata;
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wire bridge_hready_resp;
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wire bridge_hready;
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wire bridge_hresp;
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wire [W_ADDR-1:0] bridge_haddr;
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wire bridge_hwrite;
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wire [1:0] bridge_htrans;
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wire [2:0] bridge_hsize;
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wire [2:0] bridge_hburst;
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wire [3:0] bridge_hprot;
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wire bridge_hmastlock;
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wire [W_DATA-1:0] bridge_hwdata;
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wire [W_DATA-1:0] bridge_hrdata;
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ahbl_splitter #(
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.N_PORTS (2),
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.ADDR_MAP (64'h40000000_00000000),
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.ADDR_MASK (64'he0000000_e0000000)
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) splitter_u (
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.clk (clk),
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.rst_n (rst_n),
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.src_hready_resp (proc_hready ),
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.src_hready (proc_hready ),
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.src_hresp (proc_hresp ),
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.src_haddr (proc_haddr ),
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.src_hwrite (proc_hwrite ),
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.src_htrans (proc_htrans ),
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.src_hsize (proc_hsize ),
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.src_hburst (proc_hburst ),
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.src_hprot (proc_hprot ),
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.src_hmastlock (proc_hmastlock),
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.src_hwdata (proc_hwdata ),
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.src_hrdata (proc_hrdata ),
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.dst_hready_resp ({bridge_hready_resp , sram0_hready_resp}),
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.dst_hready ({bridge_hready , sram0_hready }),
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.dst_hresp ({bridge_hresp , sram0_hresp }),
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.dst_haddr ({bridge_haddr , sram0_haddr }),
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.dst_hwrite ({bridge_hwrite , sram0_hwrite }),
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.dst_htrans ({bridge_htrans , sram0_htrans }),
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.dst_hsize ({bridge_hsize , sram0_hsize }),
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.dst_hburst ({bridge_hburst , sram0_hburst }),
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.dst_hprot ({bridge_hprot , sram0_hprot }),
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.dst_hmastlock ({bridge_hmastlock , sram0_hmastlock }),
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.dst_hwdata ({bridge_hwdata , sram0_hwdata }),
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.dst_hrdata ({bridge_hrdata , sram0_hrdata })
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);
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// APB layer
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wire bridge_psel;
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wire bridge_penable;
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wire bridge_pwrite;
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wire [15:0] bridge_paddr;
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wire [31:0] bridge_pwdata;
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wire [31:0] bridge_prdata;
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wire bridge_pready;
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wire bridge_pslverr;
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wire uart_psel;
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wire uart_penable;
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wire uart_pwrite;
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wire [15:0] uart_paddr;
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wire [31:0] uart_pwdata;
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wire [31:0] uart_prdata;
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wire uart_pready;
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wire uart_pslverr;
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wire timer_psel;
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wire timer_penable;
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wire timer_pwrite;
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wire [15:0] timer_paddr;
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wire [31:0] timer_pwdata;
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wire [31:0] timer_prdata;
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wire timer_pready;
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wire timer_pslverr;
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|
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ahbl_to_apb apb_bridge_u (
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.clk (clk),
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.rst_n (rst_n),
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|
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.ahbls_hready (bridge_hready),
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.ahbls_hready_resp (bridge_hready_resp),
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.ahbls_hresp (bridge_hresp),
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.ahbls_haddr (bridge_haddr),
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.ahbls_hwrite (bridge_hwrite),
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.ahbls_htrans (bridge_htrans),
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.ahbls_hsize (bridge_hsize),
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.ahbls_hburst (bridge_hburst),
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|
.ahbls_hprot (bridge_hprot),
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.ahbls_hmastlock (bridge_hmastlock),
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.ahbls_hwdata (bridge_hwdata),
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.ahbls_hrdata (bridge_hrdata),
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|
|
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.apbm_paddr (bridge_paddr),
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.apbm_psel (bridge_psel),
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.apbm_penable (bridge_penable),
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|
.apbm_pwrite (bridge_pwrite),
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.apbm_pwdata (bridge_pwdata),
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.apbm_pready (bridge_pready),
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.apbm_prdata (bridge_prdata),
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.apbm_pslverr (bridge_pslverr)
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);
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|
|
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apb_splitter #(
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.N_SLAVES (3),
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.ADDR_MAP (48'h4000_0000_8000),
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.ADDR_MASK (48'hc000_c000_c000)
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) inst_apb_splitter (
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.apbs_paddr (bridge_paddr),
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.apbs_psel (bridge_psel),
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|
.apbs_penable (bridge_penable),
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|
.apbs_pwrite (bridge_pwrite),
|
|
.apbs_pwdata (bridge_pwdata),
|
|
.apbs_pready (bridge_pready),
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|
.apbs_prdata (bridge_prdata),
|
|
.apbs_pslverr (bridge_pslverr),
|
|
|
|
.apbm_paddr ({uart_paddr , timer_paddr, gp_paddr }),
|
|
.apbm_psel ({uart_psel , timer_psel, gp_psel }),
|
|
.apbm_penable ({uart_penable , timer_penable, gp_penable}),
|
|
.apbm_pwrite ({uart_pwrite , timer_pwrite, gp_pwrite }),
|
|
.apbm_pwdata ({uart_pwdata , timer_pwdata, gp_pwdata }),
|
|
.apbm_pready ({uart_pready , timer_pready, gp_pready }),
|
|
.apbm_prdata ({uart_prdata , timer_prdata, gp_prdata }),
|
|
.apbm_pslverr ({uart_pslverr , timer_pslverr, gp_pslverr})
|
|
);
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Memory and peripherals
|
|
|
|
// No preloaded bootloader -- just use the debugger! (the processor will
|
|
// actually enter an infinite crash loop after reset if memory is
|
|
// zero-initialised so don't leave the little guy hanging too long)
|
|
|
|
ahb_sync_sram #(
|
|
.DEPTH (SRAM_DEPTH)
|
|
) sram0 (
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.ahbls_hready_resp (sram0_hready_resp),
|
|
.ahbls_hready (sram0_hready),
|
|
.ahbls_hresp (sram0_hresp),
|
|
.ahbls_haddr (sram0_haddr),
|
|
.ahbls_hwrite (sram0_hwrite),
|
|
.ahbls_htrans (sram0_htrans),
|
|
.ahbls_hsize (sram0_hsize),
|
|
.ahbls_hburst (sram0_hburst),
|
|
.ahbls_hprot (sram0_hprot),
|
|
.ahbls_hmastlock (sram0_hmastlock),
|
|
.ahbls_hwdata (sram0_hwdata),
|
|
.ahbls_hrdata (sram0_hrdata)
|
|
);
|
|
|
|
uart_mini uart_u (
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.apbs_psel (uart_psel),
|
|
.apbs_penable (uart_penable),
|
|
.apbs_pwrite (uart_pwrite),
|
|
.apbs_paddr (uart_paddr),
|
|
.apbs_pwdata (uart_pwdata),
|
|
.apbs_prdata (uart_prdata),
|
|
.apbs_pready (uart_pready),
|
|
.apbs_pslverr (uart_pslverr),
|
|
|
|
.rx (uart_rx),
|
|
.tx (uart_tx),
|
|
.cts (1'b0),
|
|
.rts (/* unused */),
|
|
.irq (uart_irq),
|
|
.dreq (/* unused */)
|
|
);
|
|
|
|
// Microsecond timebase for timer
|
|
|
|
reg [$clog2(CLK_MHZ)-1:0] timer_tick_ctr;
|
|
reg timer_tick;
|
|
|
|
always @ (posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
timer_tick_ctr <= {$clog2(CLK_MHZ){1'b0}};
|
|
timer_tick <= 1'b0;
|
|
end else begin
|
|
if (|timer_tick_ctr) begin
|
|
timer_tick_ctr <= timer_tick_ctr - 1'b1;
|
|
end else begin
|
|
timer_tick_ctr <= CLK_MHZ - 1;
|
|
end
|
|
timer_tick <= ~|timer_tick_ctr;
|
|
end
|
|
end
|
|
|
|
hazard3_riscv_timer timer_u (
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.psel (timer_psel),
|
|
.penable (timer_penable),
|
|
.pwrite (timer_pwrite),
|
|
.paddr (timer_paddr),
|
|
.pwdata (timer_pwdata),
|
|
.prdata (timer_prdata),
|
|
.pready (timer_pready),
|
|
.pslverr (timer_pslverr),
|
|
|
|
.dbg_halt (&hart_halted),
|
|
|
|
.tick (timer_tick),
|
|
|
|
.timer_irq (timer_irq)
|
|
);
|
|
|
|
endmodule
|