Colin
|
7d927cbe73
|
delete unused file in example_soc/fpga
|
2025-04-06 17:41:26 +08:00 |
|
Colin
|
3255e9e952
|
Pass ECP5 fpga and jlink debug core.
|
2025-04-02 10:41:27 +08:00 |
|
Colin
|
b188194887
|
Add led output, refine io plan.
|
2025-04-01 18:11:04 +08:00 |
|
Colin
|
bf0e102e90
|
Add synth support.
|
2025-03-31 19:10:52 +08:00 |
|
Colin
|
aaad0d85a5
|
Enable aph port off soc, and print prints.
|
2025-03-27 23:48:10 +08:00 |
Luke Wren
|
8721bd3deb
|
Add RISC-V timer to example soc, and tweak ULX3S config
|
2022-10-07 03:11:36 +01:00 |
|
Luke Wren
|
3ae843034d
|
Example soc: connect up power signals and always-on clock. Set more parameters explicitly.
|
2022-09-04 23:42:48 +01:00 |
|
Luke Wren
|
bf38d93d33
|
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
|
2022-08-28 14:15:20 +01:00 |
|
Luke Wren
|
15cb21ae43
|
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
|
2022-08-07 20:51:12 +01:00 |
|
Luke Wren
|
b1225c386c
|
Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
|
2022-07-03 17:57:03 +01:00 |
|
Luke Wren
|
e68d8a6cd6
|
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
|
2022-06-13 01:23:32 +01:00 |
|
Luke Wren
|
5f4127948d
|
Add a parameter to control register file reset, instead of the weird ifdef tree
|
2022-05-23 13:29:44 +01:00 |
|
Luke Wren
|
b0d28447ab
|
New license headers: DWTFPL -> Apache 2.0
|
2021-12-13 23:23:40 +00:00 |
|
Luke Wren
|
1fa773c67a
|
Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently.
|
2021-12-05 02:16:54 +00:00 |
|
Luke Wren
|
5e17bb805e
|
Add basic support for lr/sc instructions from the A extension
|
2021-12-04 15:02:31 +00:00 |
|
Luke Wren
|
be6b2f3f76
|
Fix up DTMs to use byte addressing
|
2021-12-02 02:05:23 +00:00 |
|
Luke Wren
|
1ebccb7cce
|
Switch DM to use byte addresses on APB, not word addresses
|
2021-12-02 01:47:30 +00:00 |
|
Luke Wren
|
94a3d43f27
|
Add Hazard3's registered marchid value to hdl and docs
|
2021-11-28 19:53:49 +00:00 |
|
Luke Wren
|
8398d7ecb6
|
Hook up Zb* extension params on iCEBreaker FPGA
|
2021-11-26 01:44:57 +00:00 |
|
Luke Wren
|
60f364e561
|
Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
|
2021-11-21 15:55:52 +00:00 |
|
Luke Wren
|
9173bcf585
|
Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
|
2021-08-21 17:04:15 +01:00 |
|
Luke Wren
|
70a44d9681
|
Small code cleanup
|
2021-07-24 10:08:27 +01:00 |
|
Luke Wren
|
115cb2c50f
|
Tweaks to example soc configuration
|
2021-07-23 23:08:23 +01:00 |
|
Luke Wren
|
2ae30183aa
|
Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
|
2021-07-23 18:32:47 +01:00 |
|
Luke Wren
|
41477ce479
|
Extract DTM bus/control logic from the JTAG-related parts
|
2021-07-22 19:26:25 +01:00 |
|
Luke Wren
|
14ba030271
|
Example soc tweaks, add openocd config
|
2021-07-16 20:44:25 +01:00 |
|
Luke Wren
|
f4952ab66d
|
Add simple example SoC, hangs nextpnr for some reason!
|
2021-07-13 03:40:06 +01:00 |