Luke Wren 185194973f Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains		2022-08-06 23:02:08 +01:00
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bitmanip-random	Add Zbkb to bitmanip tests and regenerate vectors	2022-05-21 17:15:46 +01:00
common	Add tests for execution of mret and wfi in U mode	2022-05-24 22:14:20 +01:00
coremark	Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)	2022-07-30 17:31:53 +01:00
dhrystone	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
embench	Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)	2022-07-30 17:31:53 +01:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
riscv-compliance	Remove the halfword fetch thing, was only really useful on RISCBoy	2022-04-02 10:54:16 +01:00
riscv-tests	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
sw_testcases	Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains	2022-08-06 23:02:08 +01:00
tb_cxxrtl	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00