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arith
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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debug
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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peri
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3.f
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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hazard3_config.vh
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Support up to 128 IRQs
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2022-03-13 09:27:43 +00:00 |
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hazard3_config_inst.vh
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3_core.v
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Fix bad timing of predecoded regnum register update (thanks BMC)
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2022-04-02 10:11:55 +01:00 |
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hazard3_cpu_1port.v
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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hazard3_cpu_2port.v
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3_csr.v
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Typo -- fully encode all 128 possible IRQs
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2022-03-15 09:01:55 +00:00 |
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hazard3_decode.v
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Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
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2022-03-02 18:35:16 +00:00 |
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hazard3_frontend.v
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Remove the halfword fetch thing, was only really useful on RISCBoy
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2022-04-02 10:54:16 +01:00 |
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hazard3_instr_decompress.v
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3_ops.vh
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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hazard3_regfile_1w2r.v
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Fix forward reference to net
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2022-01-18 23:02:39 +00:00 |
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hazard3_width_const.vh
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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rv_opcodes.vh
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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