Luke Wren 66965ac073 Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted		2022-05-28 15:36:21 +01:00
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formal	Add new bus signals on instruction_fetch_match/tb.v	2022-05-27 21:48:45 +01:00
sim	Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted	2022-05-28 15:36:21 +01:00
.gitignore	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00