Luke Wren 66965ac073 Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted		2022-05-28 15:36:21 +01:00
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bitmanip-random	Add Zbkb to bitmanip tests and regenerate vectors	2022-05-21 17:15:46 +01:00
common	Add tests for execution of mret and wfi in U mode	2022-05-24 22:14:20 +01:00
coremark	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
dhrystone	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
embench	Fix remaining fallout from tb args change	2021-12-11 09:53:39 +00:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
riscv-compliance	Remove the halfword fetch thing, was only really useful on RISCBoy	2022-04-02 10:54:16 +01:00
riscv-tests	Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat	2022-05-28 15:01:27 +01:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Couple of fixups for rvpy which I forgot to commit at some point	2022-03-01 20:27:18 +00:00
sw_testcases	Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted	2022-05-28 15:36:21 +01:00
tb_cxxrtl	Add testbench flag to propagate CPU return code to testbench return	2022-05-28 15:00:28 +01:00