Luke Wren 6d55cd2d55 Consolidate openocd and bin-load testbenches		2021-12-11 09:46:38 +00:00
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bitmanip-random	Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation	2021-11-27 17:19:41 +00:00
common	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
coremark	Move DM data0 CSR into the M-custom space, and document this	2021-11-28 15:52:52 +00:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
embench	Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.	2021-12-04 01:17:57 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
riscv-compliance	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
riscv-tests	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Correct mnemonic when logging unsigned sltiu instruction	2021-10-08 12:02:37 +01:00
sw_testcases	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
tb_cxxrtl	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00