Luke Wren 7d370292b0 Fix transposition of RWX <-> XWR in PMP implementation. ... None of upstream tests used for Hazard3 seem to cover X != R. The Hazard3 tests covered this case, but the header file for the tests has the same mistake. Fix the header.		2024-04-27 13:52:43 +01:00
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bitmanip-random	Add support for testcase return code propagation to rvcpp.	2024-03-20 01:05:24 +00:00
common	Limit multilib-gen-gen to more-useful ISA combinations	2023-11-30 05:32:39 +00:00
coremark	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
dhrystone	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
embench	Update embench config and readme	2023-03-31 03:02:06 +01:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
riscv-compliance	Fix +x permission of riscv-compliance/clean_all script	2023-04-01 04:42:15 +01:00
riscv-tests	Capture JTAG bitbang log from most recent SMP debug test.	2023-03-31 02:16:23 +01:00
rvcpp	Add basic PMP implementation to rvcpp. Seems like the RWX vs XWR order might be transposed in both the hardware and the tests	2024-04-27 13:38:10 +01:00
rvpy	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
sw_testcases	Fix transposition of RWX <-> XWR in PMP implementation.	2024-04-27 13:52:43 +01:00
tb_cxxrtl	Update tb for new cxxrtl debug_info API	2024-03-17 05:32:47 +00:00