Hazard3/test/sim/sw_testcases
Luke Wren 5aee830ac0 Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
..
include Add simple test to read, write and lock PMP registers 2022-05-25 02:05:24 +01:00
.gitignore Add test script to make it easier to add software testcases 2021-12-09 22:25:18 +00:00
Makefile Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH 2023-03-31 01:53:28 +01:00
Readme.md Update readme for runtests 2022-05-30 01:12:16 +01:00
amo_fault.c Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs. 2021-12-12 18:28:23 +00:00
amo_misalign.c Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs. 2021-12-12 18:28:23 +00:00
amo_smoke.c Move expected_output into tests inline 2021-12-11 16:58:25 +00:00
amo_smoke.gtkw Add test script to make it easier to add software testcases 2021-12-09 22:25:18 +00:00
amo_timer_irq.c Add test script to make it easier to add software testcases 2021-12-09 22:25:18 +00:00
amo_timer_irq.gtkw Illegal instruction test 2021-12-10 00:11:18 +00:00
cleantests Add test script to make it easier to add software testcases 2021-12-09 22:25:18 +00:00
csr_id.c Fix misa value in csr_id test 2022-05-26 00:48:12 +01:00
csr_mcycle.c Similarly for minstret 2021-12-11 22:25:12 +00:00
csr_minstret.c Similarly for minstret 2021-12-11 22:25:12 +00:00
csr_readable.c First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested. 2022-08-22 08:47:03 +01:00
csr_readable_umode.c Update CSR readability/writability tests for new CSRs 2022-08-22 08:50:57 +01:00
csr_writable.c Update CSR readability/writability tests for new CSRs 2022-08-22 08:50:57 +01:00
ebreak.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
ecall_simple.c Move expected_output into tests inline 2021-12-11 16:58:25 +00:00
ecall_simple.gtkw Fix push/pop frame format, fix source regnums for mvsa01/mva01s 2023-03-20 02:35:18 +00:00
extension_xh3b.c First attempt at Zcmp 2023-03-20 00:19:23 +00:00
hellow.c Move expected_output into tests inline 2021-12-11 16:58:25 +00:00
illegal_instr.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
instr_access_fault.c Move expected_output into tests inline 2021-12-11 16:58:25 +00:00
irq_force.c First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested. 2022-08-22 08:47:03 +01:00
irq_individual_enable.c First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
irq_individual_pend.c First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
irq_preempt_set_in_irq.c Add top/bottom-half IRQ test 2022-08-10 00:09:13 +01:00
irq_set_all.c First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
irq_set_all_with_pri.c Whoops I needed that constant 2022-08-10 01:00:47 +01:00
irq_top_bottom.c First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested. 2022-08-22 08:47:03 +01:00
load_misalign_halfword.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
load_misalign_word.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
load_store_fault.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
lr_sc_bypass.c Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted 2022-05-28 15:36:21 +01:00
lr_sc_fault.c Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted 2022-05-28 15:36:21 +01:00
lr_sc_smoke.c Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted 2022-05-28 15:36:21 +01:00
lr_sc_smoke.gtkw Add test script to make it easier to add software testcases 2021-12-09 22:25:18 +00:00
mret_mpp_mprv.c Add test to check MPRV/MPP behaviour when executing an MRET 2022-05-29 19:51:19 +01:00
pmp_mprv.c Add test to check MPRV/MPP behaviour when executing an MRET 2022-05-29 19:51:19 +01:00
pmp_u_rw.c Add PMP U-mode read/write permission test 2022-05-29 18:42:44 +01:00
pmp_u_x.c ecall from U-mode has a different mcause value than ecall from M-mode 2022-05-28 12:07:29 +01:00
pmp_write_and_lock.c Add missing output to pmp_write_and_lock test 2022-05-25 15:34:28 +01:00
runtests Add spike-extracted output to zcmp_push 2023-03-20 15:37:38 +00:00
soft_irq.c Add minimal multicore launch code 2021-12-17 01:24:11 +00:00
store_misalign_halfword.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
store_misalign_word.c Add test for readability of all implemented CSRs 2021-12-11 17:50:12 +00:00
umode_mret.c Add tests for execution of mret and wfi in U mode 2022-05-24 22:14:20 +01:00
umode_wfi.c Add PMP U-mode read/write permission test 2022-05-29 18:42:44 +01:00
unblock_self_latching.c Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb. 2022-08-29 14:52:01 +01:00
wfi_loop.c Move expected_output into tests inline 2021-12-11 16:58:25 +00:00
wfi_loop_deepsleep_powerdown.c First stab at adding wake/sleep state machine 2022-08-28 19:50:04 +01:00
zcmp_irq_kill.c List Zcb/Zcmp in docs, and rebuild PDF 2023-03-22 03:04:16 +00:00
zcmp_mva01s.c Add tests for mva01s/mvsa01 2023-03-20 16:05:07 +00:00
zcmp_mvsa01.c Add tests for mva01s/mvsa01 2023-03-20 16:05:07 +00:00
zcmp_pop.c Add test covering all pop instructions 2023-03-20 18:26:29 +00:00
zcmp_push.c Add spike-extracted output to zcmp_push 2023-03-20 15:37:38 +00:00

Readme.md

Software Testcases

A smorgasbord of software testcases for various features and cases that aren't well-covered by upstream tests such as riscv-arch-test, the riscv-test end-to-end debug tests or riscv-formal. Each test consists of one C file.

Some tests have an expected text output associated with them -- the test passes if this text output matches, and main() exits with a zero return code. Other tests are completely self-checking, reporting pass/fail only with the return code from main(). This means there is no point running these tests if the processor is in a fundamentally broken state (e.g. doesn't pass ISA compliance) and can't be trusted to check itself.

For example, hellow.c:

#include "tb_cxxrtl_io.h"

/*EXPECTED-OUTPUT***************************************************************

Hello world from Hazard3 + CXXRTL!

*******************************************************************************/

int main() {
	tb_puts("Hello world from Hazard3 + CXXRTL!\n");
	return 0;
}

The contents of the EXPECTED-OUTPUT comment is simply compared with the logged text from tb_puts, tb_printf etc. Tests might log a range of output here, such as mcause values in exceptions. The contents of this comment may have inline // comments embedded within, and these are stripped by the test script before comparing with the output. This is useful if some of the test output requires some brief inline explanation in the test source.

To run the tests:

./runtests

This will first rebuild the simulator (../tb_cxxrtl/) if needed, then build and run all the software testcases, then print out a summary of test pass/fail status. The ./run_tests executable itself returns a successful exit code if and only if all tests passed. A printf log will be created for each test, with the same name as the test, at tmp/test_name.log.

VCD waveform dumping is not enabled by default, because tests run faster without waves, and dumping waves for all tests uses gigabytes of disk space. To re-run a failing test testname and get wave output, run:

./runtests testname --vcd

This creates a VCD file at tmp/testname_run.vcd. If you really want, you can pass --vcd without naming specific tests, to generate waves for all tests.

To clean up the junk:

./cleantests