Hazard3/test/sim
Luke Wren a9ba69f4dd Better default flags for CoreMark 2024-06-02 10:25:07 +01:00
..
bitmanip-random Add support for testcase return code propagation to rvcpp. 2024-03-20 01:05:24 +00:00
common Disable zcmp in multilib-gen-gen for now, as it is still not supported in latest binutils release 2024-06-01 18:24:06 +01:00
coremark Better default flags for CoreMark 2024-06-02 10:25:07 +01:00
dhrystone Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH 2023-03-31 01:53:28 +01:00
embench Update embench config and readme 2023-03-31 03:02:06 +01:00
hello_multicore Add minimal multicore launch code 2021-12-17 01:24:11 +00:00
hellow Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH 2023-03-31 01:53:28 +01:00
riscv-compliance Fix +x permission of riscv-compliance/clean_all script 2023-04-01 04:42:15 +01:00
riscv-tests Update .gitignore in riscv-tests to ignore output of debug tests 2024-06-01 15:53:53 +01:00
rvcpp Enable -Wextra for rvcpp 2024-06-02 10:18:40 +01:00
rvpy Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench) 2022-07-06 23:53:11 +01:00
sw_testcases Set misa.b when all of Zba, Zbb and Zbs are enabled. 2024-05-11 12:13:35 +01:00
tb_cxxrtl Do not rely on environment variables for any intra-project paths 2024-05-27 16:53:06 +01:00
project_paths.mk Do not rely on environment variables for any intra-project paths 2024-05-27 16:53:06 +01:00