Luke Wren fcbc4f6805 Fix regnum predecode of quadrant-2 RVC instructions with 5-bit regnums ... (regression caused by adding Zcb)		2023-03-21 23:04:17 +00:00
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arith	Remove op_b (rs2) register from muldiv_seq for modest LUT/FF savings	2022-10-08 18:22:16 +01:00
debug	Fix 3 minor Debug Module bugs:	2023-03-03 13:24:31 +00:00
hazard3.f	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_config.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
hazard3_config_inst.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
hazard3_core.v	Fix trap address correction for Zcm instructions never firing	2023-03-20 18:38:28 +00:00
hazard3_cpu_1port.v	First stab at adding wake/sleep state machine	2022-08-28 19:50:04 +01:00
hazard3_cpu_2port.v	First stab at adding wake/sleep state machine	2022-08-28 19:50:04 +01:00
hazard3_csr.v	Cut through-path on reset halt request from debug module to bus	2023-01-19 13:47:02 +00:00
hazard3_csr_addr.vh	First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.	2022-08-22 08:47:03 +01:00
hazard3_decode.v	Fix hookup of uop_atomic signal	2023-03-20 02:40:49 +00:00
hazard3_frontend.v	Fix regnum predecode of quadrant-2 RVC instructions with 5-bit regnums	2023-03-21 23:04:17 +00:00
hazard3_instr_decompress.v	Fix incorrect register order within stack frame for push/pop	2023-03-20 06:32:20 +00:00
hazard3_irq_ctrl.v	Tidy up priority tie-offs in irq_ctrl	2022-10-08 16:25:05 +01:00
hazard3_ops.vh	Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains	2022-08-06 23:02:08 +01:00
hazard3_pmp.v	Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.	2022-10-05 23:53:04 +01:00
hazard3_power_ctrl.v	Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep.	2022-11-05 18:26:56 +00:00
hazard3_regfile_1w2r.v	Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression	2022-09-04 23:56:14 +01:00
hazard3_triggers.v	Doh	2022-09-08 15:11:24 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00