fcbc4f6805
Fix regnum predecode of quadrant-2 RVC instructions with 5-bit regnums
...
(regression caused by adding Zcb)
2023-03-21 23:04:17 +00:00
670099e461
Fix trap address correction for Zcm instructions never firing
2023-03-20 18:38:28 +00:00
7607dacfc4
Fix incorrect register order within stack frame for push/pop
2023-03-20 06:32:20 +00:00
8b73b1b927
Fix mvsa01 r2s decode, Dhrystone runs with Zcb now
2023-03-20 05:03:39 +00:00
c4e0c15160
Fix hookup of uop_atomic signal
2023-03-20 02:40:49 +00:00
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
4aed15540d
Fix destination register for final uop of c.popretz
2023-03-20 01:31:49 +00:00
6b8923a623
Fix bad predecode of a0/a1 in mvsa01/mva01s.
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Fix bad pop load offset when extra sp adjust is nonzero.
2023-03-20 01:03:49 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
99c0660c3e
Fix decompress of c.sb/c.sh
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Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler
with Zcb enabled.
2023-03-16 20:36:36 +00:00
59edb2fc5f
Fix predecode of quadrant-00 compressed instruction rs1,
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to get correct rs1 for new Zbc byte/halfword load/store
2023-03-16 19:10:43 +00:00
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
ba3c3138ef
Fix 3 minor Debug Module bugs:
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- sbdata0 should ignore writes when sbbusyerror or sberror is set
- All sbaddress0 writes and sbdata0 accesses should set
sbbusyerror if sbbusy is set
- sbaddress should not increment if access gets bus error
2023-03-03 13:24:31 +00:00
7101cccf3b
Cut through-path on reset halt request from debug module to bus
2023-01-19 13:47:02 +00:00
52e665fb45
Remove unnecessary clear of sleep flags on bus error (which had a
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TODO asking if it should be removed) and add some more properties
in its place.
2022-11-05 18:50:41 +00:00
05cb6e7ee8
Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep.
2022-11-05 18:26:56 +00:00
c81666177e
Remove FIXME about considering concurrent load/store and debug entry
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in calculating the privilege of load/stores. This is safe because it
is only the *current* debug mode state which affects load/stores,
and some new properties have been added to ensure load/stores can
not be in aphase at the point debug mode is entered/exited (which
is achieved by delaying the trap). Therefore there is no way for
debug entry to inadvertently boost the privilege of an executing
U-mode load/store.
Also rename a confusingly-named signal for an unsquashable bus
transfer in stage 2 that delays IRQ entry.
2022-11-05 18:19:14 +00:00
97bf2d06f6
Hold off first instruction fetch until pwrup_ack is first seen high
2022-11-05 14:58:47 +00:00
1953773ca5
Don't gate exception into D-mode CSR write, as a valid CSR instruction
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writing to a valid CSR in D-mode is guaranteed not to raise any exception
(particularly the external data0 CSR is of interest)
2022-10-10 22:15:56 +01:00
ae4ddf7001
Clean up the old/unused W_COUNTER parameter, and use a cleaner tie-off style for the counter CSRs
2022-10-10 16:33:31 +01:00
f771a1294d
Alias DPC to the real program counter, small savings overall
2022-10-10 00:28:42 +01:00
aa438fc37c
Remove op_b (rs2) register from muldiv_seq for modest LUT/FF savings
2022-10-08 18:22:16 +01:00
d3667769d2
Arrange for address buses to be 0 when processor is held in reset
2022-10-08 16:50:58 +01:00
633a07fef9
Tidy up priority tie-offs in irq_ctrl
2022-10-08 16:25:05 +01:00
5e7bf0d604
Don't reset register file by default
2022-10-08 16:24:28 +01:00
489480dc80
Revise default config values, and update docs with new values
2022-10-08 08:43:25 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
bf1bca2ca5
Remove FPGA synth netlist checked in by mistake
2022-10-06 16:00:27 +01:00
1036d15467
Clean up duplicate declaration of external_irq_pending in hazard3_irq_ctrl
2022-10-06 15:59:54 +01:00
e6aaf4b801
Avoid IRQ to bus through-path when custom IRQs are disabled
2022-10-06 00:16:10 +01:00
c55d3f0d0b
Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.
2022-10-05 23:53:04 +01:00
d1d70efa60
Fix some width issues introduced by last commit
2022-10-05 22:19:02 +01:00
6f8b75c041
Make IRQ vectors right-sized. CXXRTL was spending > 1/3rd of its time in the CSR update.
2022-10-05 22:11:53 +01:00
0915cc2834
Doh
2022-09-08 15:11:24 +01:00
9eb8590858
Add generate to avoid elaborating internals of PMP/triggers with 0 PMP regions or triggers.
2022-09-05 00:36:41 +01:00
18c64bd633
Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression
2022-09-04 23:56:14 +01:00
787a7ec372
Fix bad preprocessor conditional in ECP5 JTAG DTM
2022-09-04 23:48:58 +01:00
c594ec42e9
Change style of IRQ register tie-offs as Yosys was not able to trim them for iCE40 synthesis.
2022-09-04 23:43:24 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
1c2249dbef
Typo
2022-08-29 16:25:12 +01:00
6abd93eb49
Oops, masked the wakeup-on-halt request path when I masked IRQs on WFI state.
2022-08-29 16:15:19 +01:00
099f0467fb
Clean up remnants of the 'wfi_is_nop' thing that seemed like a good idea at the time
2022-08-29 15:56:57 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
9a60f06c43
Fix trigger enable condition
2022-08-23 01:05:46 +01:00
fef6d80fd4
tcontrol.mpte is not supposed to change on trap exit, unlike mstatus.mpie
2022-08-23 00:19:56 +01:00
9e11c0e5a8
Fix tdata1.dmode being writable from M-mode
2022-08-23 00:08:17 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
49c2edeff8
Avoid reserved keyword
2022-08-22 10:26:20 +01:00
Luke Wren