Luke Wren ca40c077be Capture JTAG bitbang log from most recent SMP debug test. ... Regarding intermittent failure of SMP debug MemorySampleSingle test: https://twitter.com/wren6991/status/1640153934445543426 Seems to be an OpenOCD issue, not a Hazard3 issue.		2023-03-31 02:16:23 +01:00
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bitmanip-random	Add Zbkb to bitmanip tests and regenerate vectors	2022-05-21 17:15:46 +01:00
common	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
coremark	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
dhrystone	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
embench	Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)	2022-07-30 17:31:53 +01:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
riscv-compliance	Update to the latest riscv-arch-test. This uses the new test	2023-03-31 01:39:48 +01:00
riscv-tests	Capture JTAG bitbang log from most recent SMP debug test.	2023-03-31 02:16:23 +01:00
rvcpp	Fix mvsa01/mva01s in rvcpp	2023-03-21 21:54:04 +00:00
rvpy	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
sw_testcases	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
tb_cxxrtl	tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ	2023-03-31 02:11:52 +01:00