Luke Wren d31b1708db Make rvpy cycle-accurate enough to get the correct Dhrystone score		2022-06-09 01:34:37 +01:00
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bitmanip-random	Add Zbkb to bitmanip tests and regenerate vectors	2022-05-21 17:15:46 +01:00
common	Add tests for execution of mret and wfi in U mode	2022-05-24 22:14:20 +01:00
coremark	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
dhrystone	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
embench	Fix remaining fallout from tb args change	2021-12-11 09:53:39 +00:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Add zicsr to march in makefiles	2022-05-24 16:17:54 +01:00
riscv-compliance	Remove the halfword fetch thing, was only really useful on RISCBoy	2022-04-02 10:54:16 +01:00
riscv-tests	Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.	2022-05-28 17:22:28 +01:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Make rvpy cycle-accurate enough to get the correct Dhrystone score	2022-06-09 01:34:37 +01:00
sw_testcases	Remove stray old expected output file from sw_testcases dir	2022-06-03 17:20:49 +01:00
tb_cxxrtl	Add testbench flag to propagate CPU return code to testbench return	2022-05-28 15:00:28 +01:00