Luke Wren e89ab0d095 tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ ... (i.e. single-core testbench). Avoids some odd behaviour with wide assignment to single-bit wire from the CXXRTL harness.		2023-03-31 02:11:52 +01:00
..
.gitignore	tb_cxxrtl Makefile: better support for building multiple tb configurations	2023-03-24 18:44:37 +00:00
Makefile	tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ	2023-03-31 02:11:52 +01:00
compliance.cfg	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
config_default.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
config_min.vh	First attempt at Zcmp	2023-03-20 00:19:23 +00:00
gdbinit	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
multicore-openocd.cfg	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
multicore.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
openocd.cfg	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
tb.cpp	tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ	2023-03-31 02:11:52 +01:00
tb.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb.v	tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ	2023-03-31 02:11:52 +01:00
tb_common.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb_multicore.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb_multicore.v	Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.	2023-03-26 23:00:18 +01:00
waves.gtkw	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00