Luke Wren b7d9defcf2 Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3		2022-07-05 03:37:19 +01:00
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arith	Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3	2022-07-05 03:37:19 +01:00
debug	Ignore read data from failed SBA accesses	2022-07-03 20:58:01 +01:00
hazard3.f	Integrate PMP, and fix a couple of PMP bugs	2022-05-24 19:57:45 +01:00
hazard3_config.vh	Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3	2022-07-05 03:37:19 +01:00
hazard3_config_inst.vh	Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3	2022-07-05 03:37:19 +01:00
hazard3_core.v	Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3	2022-07-05 03:37:19 +01:00
hazard3_cpu_1port.v	Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core	2022-07-03 18:02:47 +01:00
hazard3_cpu_2port.v	Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core	2022-07-03 18:02:47 +01:00
hazard3_csr.v	Clear local monitor on non-debug trap entry/exit	2022-06-26 21:55:51 +01:00
hazard3_csr_addr.vh	Add menvcfg CSR, and comment explaining why we don't have mseccfg CSR	2022-06-26 01:25:48 +01:00
hazard3_decode.v	Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,	2022-06-25 20:08:40 +01:00
hazard3_frontend.v	Typo	2022-07-04 12:09:21 +01:00
hazard3_instr_decompress.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_ops.vh	ecall from U-mode has a different mcause value than ecall from M-mode	2022-05-28 12:07:29 +01:00
hazard3_pmp.v	Clean up tie-off of hardwired PMP registers	2022-07-04 14:31:42 +01:00
hazard3_regfile_1w2r.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	Correct the name and operation of the brev8 (formerly rev.b) instruction	2022-05-20 15:28:18 +01:00