Luke Wren fadb9601de Illegal instruction test		2021-12-10 00:11:18 +00:00
..
bitmanip-random	Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation	2021-11-27 17:19:41 +00:00
common	Add test script to make it easier to add software testcases	2021-12-09 22:25:18 +00:00
coremark	Move DM data0 CSR into the M-custom space, and document this	2021-11-28 15:52:52 +00:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
embench	Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.	2021-12-04 01:17:57 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
openocd	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
riscv-compliance	Bump to latest version of riscv-arch-test	2021-12-06 02:18:48 +00:00
riscv-tests	Update riscv-tests for correct misa.x value	2021-12-04 11:19:43 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Correct mnemonic when logging unsigned sltiu instruction	2021-10-08 12:02:37 +01:00
sw_testcases	Illegal instruction test	2021-12-10 00:11:18 +00:00
tb_cxxrtl	Add test script to make it easier to add software testcases	2021-12-09 22:25:18 +00:00