graph compile will crash when shape is broadcast from 1 to 1,1,1,1
Type: Bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
Modify tolerance in some of these op unit tests for StreamProcessor
Type: Bug Fix
Issue: 37103
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
1.Skip elementwise/relational op unittest if input/output have INF which sp cannot
handle
2.Set different tolerance in Layernom/SoftMax/GRU unittest if SP supported
Type: Bug Fix
Issue: 37103
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added SetScalar api to support scalar input
Added 2 cases for scalar index Gather
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Resolve the issue of underlying hardware not supporting float16 bias in fc
by converting bias type to float32
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Only NNAPI instance norm spec have scalar gamma and beta, which can not
support by sp, rewrite it into tensor.
Type: Bug Fix
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
* Refine api trace code and document
Add missing traced apis of tim::vx::Quantization
Type: Code improvement
* Split Api relayer code out of tracer.
To enable compile replayer code in machine which can't access high version boost libs.
Type: Code improvement
Correct erros of deconv1d unittest
Added hint in the header indicating that padtype is not supported yet
Added 2 cases for deconv1d
Type: Code Improvement
Issue: github issue #585
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
* Refine api trace code and document
Add missing traced apis of tim::vx::Quantization
Type: Code improvement
1.Added copyright && Added reference or const reference for functions
2.Rewrite function of determing whether there is a common input
3.Use std::remove_if instead of std::find before doing erase
4.Added security check to prevent access to deleted ops
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added Float16 type definition from third-party
Refine float16 bias handlling in conv2d
Refine float16 case in conv2d
Caution: Headers of float16 only be included when build unit_test
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added op fusion for mean_stddev_normalization ops such as layernorm and
instance norm
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
If Executable object doesn't bind with a concrete DeviceID,
it will go first device by default.
When run multi executable with multi device, the behavior is not
expected. Fixed by attach device id with CompileOption.
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Fixed bug that when deconv1d ouput is set to be transient, actual output shape will be zero at dim 1.
Reason :internal typing error
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver
Caution: Clang version requires minimum 15.0
Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Add another constructor for stridedslice when new_axis_mask is set
The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Remove unused value to make sure project build successfully with higher
version compiler such as clang15
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
chxin66
Chen Feiyue
xie-oritek
Antkillerfarm
Zhouheng Zheng
MercuryChen
zhongzhuonan
Sven