Correct erros of deconv1d unittest
Added hint in the header indicating that padtype is not supported yet
Added 2 cases for deconv1d
Type: Code Improvement
Issue: github issue #585
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added Float16 type definition from third-party
Refine float16 bias handlling in conv2d
Refine float16 case in conv2d
Caution: Headers of float16 only be included when build unit_test
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver
Caution: Clang version requires minimum 15.0
Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Add another constructor for stridedslice when new_axis_mask is set
The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Refine unidirectional_gru and gru_cell code to avoid including ovxlib files
in header of some op
Introduce TranslateToVsibool function to support above code refinement
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added missing ops which have already supported; Changed status of some
ops.
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Fixed the IOtensor order difference between src_graph and infer_graph
Graph Input/Output tensor sequence may changed after graph
transformation(layout infer), it is difficult to get the IO mapping
between original graph and final graph.
Clients such as the Android Support Library create tensors using the
original input/output order, which may not be the same as the input
order of src_graph, the data can not be setup correctly.
Solution:
Decide the order of inputs/outputs while creating tensor not at binding to
operation. The order of binding could be change in each transform.
Type:Code improvement
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
* Fixed maxpoolgrad maxpoolwithargmax2 cases
Some tensors created with wrong attr
Type: Bug fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
---------
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
Type: New Feature | Bug Fix | Code Improvement | Documentation
Issue: bugzilla id | jira id #No more newline after this
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Modified datatype of copied output so that actual float16 output can be
checked correctly
Type: Bug Fix
Issue: Bug 34696
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Changed status of UnidirecitonalRnn&BidirectionalRnn
Changed status and internal op of BidirectionalLstm
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified copyright and log message
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>