Commit Graph

231 Commits

Author SHA1 Message Date
Chen Feiyue 9bb3e7c68b
Fixed misleading test case bug in deconv1d (#633)
Correct erros of deconv1d unittest
Added hint in the header indicating that padtype is not supported yet
Added 2 cases for deconv1d

Type: Code Improvement
Issue: github issue #585

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-08-17 21:26:54 +08:00
Chen Feiyue af50cc5e3f
Added general Float16 support (#631)
Added Float16 type definition from third-party
Refine float16 bias handlling in conv2d
Refine float16 case in conv2d
Caution: Headers of float16 only be included when build unit_test

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-08-12 10:04:16 +08:00
chxin66 bff26a32c4
fix size compute bug in lrn (#626)
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-08-07 13:20:35 +08:00
MercuryChen 315adcf076
Integrate api trace into tim-vx source as an experimental feature. (#623)
* Add support for different input dtype of MaxPoolGrad.

Type: Code improvement

* Integrate api trace into tim-vx source code, as part of experimeantal.

Type: New Feature
2023-07-19 18:40:48 +08:00
Chen Feiyue 0885a0d797
Remove confusing comment in depthwise conv test (#621)
Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-07-17 09:43:34 +08:00
Chen Feiyue 62c6b6560c
Added axis param for TopK (#610)
Topk support specifying dimensions with later internal ovxlib

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-07-12 09:54:07 +08:00
chxin66 ea8046ec9c
Added roi_align layoutinfer & cases (#615)
* Added roi_align layoutinfer & cases

Type: New feature

Signed-off-by: Chen <jack.chen@verisilicon.com>

* Update instancenorm op spec .json

Type: bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>

* Added roi_pool layoutinfer & fixed case bug

Type: new feature

Signed-off-by: Chen <jack.chen@verisilicon.com>

---------

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-07-08 23:39:56 +08:00
Chen Feiyue 33f3a4f176
Enable float16 bias convolution model runs on NN (#612)
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver

Caution: Clang version requires minimum 15.0

Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-30 09:41:28 +08:00
chxin66 34812fe40e
Added case for gather (#599)
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-06-26 09:15:08 +08:00
Chen Feiyue 75882d4195
Added new_axis_mask param for stridedslice (#600)
Add another constructor for stridedslice when new_axis_mask is set

The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-25 09:24:41 +08:00
Chen Feiyue fbfbdd7c83
Added axis support for layernorm (#602)
Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson

Type:  Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-15 21:45:46 +08:00
chxin66 ea8adc456a
fixed instance norm bug & add its layoutinfer (#593)
Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-31 12:55:42 +08:00
chxin66 4f92e58155
optimization for tiny_yolov4 (#591)
Type: code improvment

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-23 14:28:47 +08:00
shijie001 51faf286c2
Fixed LayerNormalization eps bug (#589) 2023-05-22 14:13:44 +08:00
chxin66 99606fd891
Add a case for local response norm (#590)
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-20 16:57:21 +08:00
chxin66 ddcb00c11b
Fixed bug for pad test (#588)
Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-05-20 16:56:00 +08:00
Chen Feiyue 3c372dd646
Refine UnidirectionalGRU and GRUCell (#587)
Refine unidirectional_gru and gru_cell code to avoid including ovxlib files
in header of some op
Introduce TranslateToVsibool function to support above code refinement

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-05-15 16:44:51 +08:00
Chen Feiyue 3a3c9fa5fa
Update readme in ops (#575)
Added missing ops which have already supported; Changed status of some
ops.

Type: Documentation

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-04-20 13:23:56 +08:00
chxin66 c2755b90ea
Fixed l2normalization layout infer bug (#570)
And added a case

Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-27 15:00:25 +08:00
chxin66 6424ef104e
Fixed the IOtensor order difference between src_graph and infer_graph
* Fixed the IOtensor order difference between src_graph and infer_graph

Graph Input/Output tensor sequence may changed after graph
transformation(layout infer), it is difficult to get the IO mapping
between original graph and final graph.

Clients such as the Android Support Library create tensors using the
original input/output order, which may not be the same as the input
order of src_graph, the data can not be setup correctly.

Solution:
Decide the order of inputs/outputs while creating tensor not at binding to
operation. The order of binding could be change in each transform.

Type:Code improvement

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

* Fixed maxpoolgrad maxpoolwithargmax2 cases

Some tensors created with wrong attr

Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

---------

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-21 09:21:15 +08:00
Chen Xin f0a0f1728a Added case for hardswish
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-06 09:37:13 +08:00
Feiyue Chen ea4ba66b94 Refine Depth2Space op
Change default mode from CRD_mode to DCR_mode

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-02-09 13:19:57 +08:00
Chen Xin 5e7f5cecea Fixed grouped_conv2d layout infer & Added cases
added cases for conv2d/grouped_conv2d

Type: Bug fixed

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-01-20 15:28:21 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Chen Xin 58d36ab943 Added reduce_all layoutinfer & reduce cases
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-01-09 09:30:44 +08:00
Feiyue Chen 789d4458ff Added 4d quantized LUT unittest for embedding_lookup
Type: New Feature | Bug Fix | Code Improvement | Documentation
Issue: bugzilla id | jira id #No more newline after this
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-01-09 09:28:45 +08:00
Feiyue Chen 06d4747b31 Fixed wrong type of hashtable_lookup unit test
Modified datatype of copied output so that actual float16 output can be
checked  correctly

Type: Bug Fix
Issue: Bug 34696
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-01-03 15:10:25 +08:00
meseraph cc34b5f0ea mapped pool1d 2022-12-30 10:52:28 +08:00
Chen Xin aa0b474c19 Added a case for fc
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-30 10:34:21 +08:00
Chen Xin 0e211c8efd Fixed (groupd)conv2d layout infer bug
And added a weight_as_input case to test

Type: Bug Fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-16 15:20:56 +08:00
Feiyue Chen 06b88e7940 Fixed nn_params in groupconv2d
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-16 15:08:14 +08:00
Chen Xin 7582b57edc Added pad_v2 & pad_v2 layout infer
And added 4 rank case

Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-16 15:03:58 +08:00
Feiyue Chen 8d8f4b6e68 Added EmbeddingLookup & deprecate LshProjection
Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-05 09:59:56 +08:00
Qin.Chen 13da73bbe3 Fix maxpoolgrad, hide unused pool value output
Type: Bug Fix
2022-12-01 15:49:38 +08:00
Feiyue Chen f7b49ae4e2 Modified README.md about rnn&lstm
Changed status of UnidirecitonalRnn&BidirectionalRnn
Changed status and internal op of BidirectionalLstm

Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-01 10:56:48 +08:00
Feiyue Chen dd7cd2504c Added HashtableLookup Op
Added HashtableLookup Op and unit test

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-01 10:55:21 +08:00
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-28 09:45:50 +08:00
Feiyue Chen 05a1c561af Added layout_inference for UnidirectionalRnn
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-23 20:58:00 +08:00
Qin.Chen 8cd5bd93ce Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now. 2022-11-22 21:39:02 +08:00
Chen Xin 545d677160 diabled a failed case
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-22 21:36:41 +08:00
Chen Xin 9fe7b955e5 Fixed average pool layout infer
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-16 13:34:31 +08:00
meseraph 883334e1bb add rnn 2022-11-16 13:33:39 +08:00
Feiyue Chen 11fd278d7a Fixed BidirectionalSequenceLSTM bug
Fixed input error of  the backward direction
Fixed golden error of unit test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-16 13:31:23 +08:00
Chen Xin 6816a0188a Added minimum unit test
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-11 18:03:46 +08:00
Chen Xin 8867c8de35 Fixed roi_align golden mismatch error
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-11 18:02:36 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-10-08 21:42:02 +08:00
Feiyue Chen a038df2a84 added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429 2022-10-08 14:47:07 +08:00
Chen Xin 20db77ee61 Added two cases in strided_slice
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-29 20:24:09 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test
Fixed fc layout infer in rnncell layout infer
2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00