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377 Commits

Author SHA1 Message Date
Kee 4db479ece4 Set RNN internal dtype 
Init RNN internal dtype to avoid the
internal FC OP to go to the CPU path

Type:Code Improvement

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-11-14 09:39:27 +08:00
Feiyue Chen b53fd14375 Update x86_64_linux/include for 22Q3 
update prebuilt-sdk/x86_64_linux/include
update VERSION file

Type:  Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-11 18:22:26 +08:00
Chen Xin 6816a0188a Added minimum unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:03:46 +08:00
Chen Xin 8867c8de35 Fixed roi_align golden mismatch error 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:02:36 +08:00
zhouheng.zheng 25c38d45e1 add custom op in lenet test 2022-10-28 17:43:01 +08:00
Feiyue Chen fde6d799ae Fixed multi_device compiling error in gcc 12 
fixed mismatched allocation error in  multi_device.cc

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:36:13 +08:00
Feiyue Chen 922d10696d Update prebuilt-sdk for 22Q3 release 
Update prebuilt-sdk for 22Q3 release

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Feiyue Chen ed162d0176 Update internal for 22Q3 release 
update internal to commit-id: e2b0fde631fce349e0e3ad42b2a4d40ce7634a97

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Feiyue Chen 7baf8c307f Fixed tensorflow version in CI 
modify fetched tensorflow version to v2.10.0

Type: Bug Fix

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-19 18:04:52 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-10-08 21:42:02 +08:00
Feiyue Chen a038df2a84 added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429 2022-10-08 14:47:07 +08:00
Chen Xin 20db77ee61 Added two cases in strided_slice 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-29 20:24:09 +08:00
Chen Xin 535c9da867 Fixed bug when input's index is not 0 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 16:48:16 +08:00
Chen Xin 4c6299e7fd Added two reduce layout infer unittest 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 09:37:38 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00
Feiyue Chen 264e491d2a added cumsum op & added handle api after BindInput 2022-09-26 14:27:48 +08:00
Feiyue Chen 9cb37b920f added MaxPool3d op 2022-09-26 13:32:56 +08:00
Feiyue Chen 8b8d09aea3 added Rcp op & modified test_utils 2022-09-22 12:15:02 +08:00
Feiyue Chen 1b07b022e2 added sign & softsign 2022-09-20 22:49:45 +08:00
Feiyue Chen f4d5e170de added & modified copyright of some files 2022-09-20 22:47:33 +08:00
Feiyue Chen 84b464ee8b Update README.md 2022-09-20 22:47:33 +08:00
Feiyue Chen 6099022f00 added Mod op & Mod unit test 2022-09-20 22:47:33 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
Feiyue Chen 113c3722cb supported int16 dfp quantization & added conv2d unit test 2022-09-15 22:15:22 +08:00
Feiyue Chen 95401036ab fixed some errs on gcc12 2022-09-15 21:26:43 +08:00
Chen Xin 6d9ed7b25b Disabled a conv3d case 
because of some branches are not fully supported

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-15 10:46:05 +08:00
Kainan Cha a6e04b2116
Update cmake_x86_vsim.yml 2022-09-09 17:24:23 +08:00
Sven a7a7e15793
Update OpenCV usage link (#477) 
https://github.com/opencv/opencv/wiki/TIM-VX-Backend-For-Running-OpenCV-On-NPU
 2022-09-07 13:14:45 +08:00
Chen Xin 0bb547b8e4 disabled two Div cases 
int32 type not supported in branch 234062
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 23:58:03 +08:00
Chen Xin e62b62015d Added conv3d unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 11:45:24 +08:00
xiang.zhang e9771746ba Fix error in feature compatiable guard 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-05 15:05:50 +08:00
Chen Xin f348c8e36c disabled two not supported cases 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-05 14:52:59 +08:00
Sven 9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable (#471) 
Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-01 18:56:49 +08:00
Chen Xin f6121140b0 Mapped unidirectional gru & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:27:05 +08:00
Chen Xin 58395cf7a7 Modified bidirectional_sequence_lstm golden accuracy 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:26:07 +08:00
root 80fed36ea3 Modified Div_int unit test golden 
Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
 2022-08-30 10:28:09 +08:00
Sven 562d0d43b0
Update Version to 1.1.50 (#462) 2022-08-22 17:41:43 +08:00
Chen Xin 1c640c6f10 Mapped bidirectional lstm & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-22 10:42:05 +08:00
Kainan Cha d4f9d7475f
Update version number to 1.1.42 2022-08-16 11:29:47 +08:00
Kee 96d186c8d2 Set graph attributes when compile graph to binary 
Keep the same graph attributes as compile graph

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-08-15 06:34:08 +08:00
qin.chen 5482760ba2 include Topk op's header file 2022-08-15 06:29:55 +08:00
Chen Xin 944fdfad8f Mapped GRUCell & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 20:34:19 +08:00
Chen Xin 03b5ec2d17 Added div int32 unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 14:37:34 +08:00
Tang a5ba633fe4 add readme for ovxlib_bin_build.sh 2022-08-08 16:52:45 +08:00
yuenan.li 9a28ff5758 Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-08-08 16:50:25 +08:00
Chen Xin 3663a99e0f Fixed param compute bug for lrn 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-04 21:35:59 +08:00
ZhangXiang f728e1b42d Update overview diagram 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
ZhangXiang 6d47ee3ac1 Expose hw feature : isClOnly() 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
ZhangXiang 090f3f21d6 Add ut configuration for cl only device 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00