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301 Commits

Author SHA1 Message Date
Sven 9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable (#471) 
Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-01 18:56:49 +08:00
Chen Xin f6121140b0 Mapped unidirectional gru & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:27:05 +08:00
Chen Xin 58395cf7a7 Modified bidirectional_sequence_lstm golden accuracy 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:26:07 +08:00
root 80fed36ea3 Modified Div_int unit test golden 
Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
 2022-08-30 10:28:09 +08:00
Chen Xin 1c640c6f10 Mapped bidirectional lstm & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-22 10:42:05 +08:00
Kee 96d186c8d2 Set graph attributes when compile graph to binary 
Keep the same graph attributes as compile graph

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-08-15 06:34:08 +08:00
Chen Xin 944fdfad8f Mapped GRUCell & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 20:34:19 +08:00
Chen Xin 03b5ec2d17 Added div int32 unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 14:37:34 +08:00
Tang a5ba633fe4 add readme for ovxlib_bin_build.sh 2022-08-08 16:52:45 +08:00
yuenan.li 9a28ff5758 Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-08-08 16:50:25 +08:00
Chen Xin 3663a99e0f Fixed param compute bug for lrn 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-04 21:35:59 +08:00
ZhangXiang 6d47ee3ac1 Expose hw feature : isClOnly() 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
Chen Xin 27b4298b29 Fixed quantize param in reduce_sum 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-29 11:12:09 +08:00
qin.chen 9ebddb5452 add op: maxpoolwithargmax2 and maxpoolgrad 2022-07-29 11:11:33 +08:00
qin.chen 84d76e5251 fixed: maxpoolwithargmax's output1 have wrong shape, internal id: I7d5aeab58038bacb73373a4ff4f48a12bb6441db 2022-07-29 11:11:33 +08:00
Antkillerfarm 32241dc4ad
Rename RoiAlign & RoiPool (#446) 2022-07-29 11:10:25 +08:00
chxin66 96c9d5df01
Added cases for reduce sum (#441) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:53:56 +08:00
chxin66 cfe8c808bd
Added broadcast layout infernece (#438) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:52:48 +08:00
liyuenan 7d88a668e3
Update internal for 22Q2 release (#432) 
* Update internal for 22Q2 release

update to internal commit-id: e96103281b08404cabb9b65306587627cfa3cb93

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

* Update prebuilt for 22Q2 release

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-07-25 09:29:22 +08:00
chxin66 9f331ed5ec
Added batch dims in gather (#435) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-19 12:33:09 +08:00
chxin66 f52cb852d6
Fixed transpose layout inference bug (#430) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:55:48 +08:00
chxin66 6344379469
Disabled 3 failed case (#428) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:54:42 +08:00
liyuenan 24fa582a56
Enable SetRoundingPolicy (#426) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-07-06 17:03:54 +08:00
chxin66 e047fce59f
Disable cases which offloaded to SW path(#422) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-04 15:37:06 +08:00
chxin66 3e8d5e3493
Added grouped conv2d layout inference (#419) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-06-28 14:52:26 +08:00
Antkillerfarm 3dd6c507d4
add reshape unit test (#416) 2022-06-23 14:07:38 +08:00
MESeraph 11f953b506
Mapped roi_pool & added unit test (#404) 
* Mapped roi_pool & added unit test

* modify roialign/roipool unit test
 2022-05-30 19:57:50 +08:00
chxin66 44cc6f9f09
lstm layout inference & Added unidirectional lstm layout inference (#392) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-29 22:40:43 +08:00
MESeraph 6d0c6b01b5
modify GatherElements (#406) 2022-05-29 22:25:14 +08:00
chxin66 1b4c30e572
Mapped roi_align & added unit test (#402) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-27 16:34:48 +08:00
Dahan Gong f8741b4704
feat(tensor): support external buffer when creating input/output tensors (#389) 
* support external buffer when creating input/output tensors

* feat(tensor): add new map/unmap APIs
 2022-05-18 23:38:26 +08:00
Sven a9764291b0
Fix build issue (#397) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-16 14:24:44 +08:00
Sven 4f2991c853
Fixed no-output if transpose is last op and can be optimized (#395) 
* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-13 16:59:25 +08:00
Antkillerfarm b3677305c4
add GetElementNum/GetElementByteSize/GetByteSize for TensorSpec (#393) 2022-05-13 14:29:25 +08:00
chxin66 0d8ac3dc2b
Added gather_elements & unit test (#363) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-10 09:55:50 +08:00
chxin66 60cfea53a0
fix gather_element operation input num issue (#388) 
Change-Id: Id2e685cf6993776e6674f528b71eb842420b16ad

 Author:    Xia Kaihong <kaihong.xia@verisilicon.com>
 Date:      Thu Apr 14 16:23:16 2022 +0800
 2022-05-06 09:31:14 +08:00
Antkillerfarm c6847981e6
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for unit test compatibility (#386) 2022-05-06 09:30:26 +08:00
chxin66 11572140d2
Fixed layout inference bug for stack (#375) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:18:09 +08:00
MESeraph eab0d807a6
Added Ceil & unit test (#381) 
* Added Ceil & unit test

* Added Round & Unit test
 2022-05-05 17:11:31 +08:00
chxin66 7a8ae32f73
Added topk & unit test (#384) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:06:39 +08:00
Zhouheng Zheng c09cdf79ad
fix bug of param num in custom op (#385) 
ref to:https://github.com/VeriSilicon/TIM-VX/issues/378

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-05-05 17:04:38 +08:00
Antkillerfarm 3f2e67b65f
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for ovxlib compatibility (#374) 2022-04-24 18:38:56 +08:00
Antkillerfarm dbb3631d4e
rename CopyTensorToData to CopyDataFromTensor to align name of tim::vx::Tensor (#373) 2022-04-24 13:36:51 +08:00
chxin66 5c4800ab33
Fixed pad layout inference bug & added one stridedslice case (#370) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-20 21:44:43 +08:00
Sven b5c4514b94
Update operator support planw (#367) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-04-19 11:38:07 +08:00
Antkillerfarm b916e1301a
Add Broadcast op (#365) 2022-04-18 15:45:15 +08:00
chxin66 96dedc1453
Added selu & celu & unit test (#366) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-18 14:35:29 +08:00
Antkillerfarm 954d264108
add BroadcastInDim to internal expand_broadcast op (#364) 2022-04-18 13:59:18 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 479fc576ae
Suported specifying CRD_mode & DCR_mode in depthtospace (#362) 
https://github.com/VeriSilicon/TIM-VX/issues/304

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:53:32 +08:00
chxin66 0dc38eac2e
Added unit test for maxpool (#361) 
https://github.com/VeriSilicon/TIM-VX/issues/318

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 22:16:47 +08:00
lucklee 12746cb4d7
refine tim_internal.cmake for ovxlib vip (#360) 2022-04-13 22:14:32 +08:00
chxin66 93f20429ea
Fixed layout inference bug for stride_slice (#329) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:12:37 +08:00
chxin66 ba6b311409
Added hardsigmoid test case with alpha and beta (#356) 
https://github.com/VeriSilicon/TIM-VX/issues/306

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:10:30 +08:00
lucklee 1eaf326abf
update ovxlib virtual_device patch (#357) 2022-04-13 10:04:46 +08:00
chxin66 c033cfc582
Fixed compiler fail for elu (#358) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 18:42:50 +08:00
chxin66 e8ca6b8ee3
Added param step for slice & added unit test (#352) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 15:42:58 +08:00
Zhouheng Zheng 20e27ed550
Update prebuilt and internal for 22Q1 release(#349) 
update driver to REL/6.4.10.2
update internal to commit-id: 33cfb75b

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-04-12 15:18:45 +08:00
chxin66 d0af7ae8df
Support alpha in elu (#354) 
https://github.com/VeriSilicon/TIM-VX/issues/305

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-11 19:04:30 +08:00
Zhouheng Zheng b4091318ea
fix buf of param init in custom op (#345) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-04-06 17:21:54 +08:00
lucklee 70d2f410a8
support virtual vip devices (#331) 2022-04-06 13:05:38 +08:00
chxin66 1ca89d2ffa
Add layout inference & layout test for stack (#337) 
* Added layout inference & layout test for stack

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-06 13:01:41 +08:00
Sven 171abb0f1b
Revert "composed Dense & added unit test (#312)" (#340) 
This reverts commit f2e71a3deb.
 2022-03-31 18:37:45 +08:00
Sven 18ce7b45fb
Enable handle support for new hardware (#334) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-29 18:12:28 +08:00
Zhouheng Zheng d1b57e8eca
Add cmake option of custom op support (#335) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-28 09:42:19 +08:00
chxin66 f2e71a3deb
composed Dense & added unit test (#312) 
if shape is 3D or larger, implement it as reshape + fc + reshape

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-03-25 10:49:39 +08:00
Kee 53291e99cf
Add ArgMax/ArgMin unit tests (#333) 
* Add ArgMax/ArgMin unit tests

https://github.com/VeriSilicon/TIM-VX/issues/330
 2022-03-25 09:46:50 +08:00
Sven 097f8d74cd
Refine customized op support (#327) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 23:00:52 +08:00
Sven 08500158ba
Fix build error with clang (#326) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 14:51:12 +08:00
Kee 2a8936dfed
Added unit test for batch2space and space2batch (#321) 2022-03-15 21:25:01 +08:00
Zhouheng Zheng 4d5013edf9
wrapper public ovxlib api (#320) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-15 21:24:15 +08:00
Zhouheng Zheng b02aa8b8c4
Added customize operator APIs(#315) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-09 12:10:08 +08:00
Zhouheng Zheng 161bb8a7c4
Pre-release for 22Q1 (#302) 
update internal to commit-id: d45da6fa

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-01 17:56:03 +08:00
Sven e63059857b
Update reshape to reshape2 (#310) 
Update built-in op reshape to reshape2

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 17:04:02 +08:00
Sven c8a25d32ad
Relax tolerance for div_uint8 case (#303) 
* Relax tolerance for Div.shape_5_1_broadcast_scale_uint8
* Add tolerance for div uint8

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 10:54:56 +08:00
chxin66 3decff5398
Added unit test for STACK (#298) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-23 22:04:54 +08:00
chxin66 242a6bd05a
Add pad value for grouped_conv1d (#292) 
https://github.com/VeriSilicon/TIM-VX/issues/284

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-21 19:11:36 +08:00
liyuenan fe31a47bf9
enable no bias in FC layout inference (#294) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-02-21 19:09:38 +08:00
Sven 6e0ac09c92
Relax tolerance for Div.shape_5_1_broadcast_scale_uint8 (#296) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-21 18:34:44 +08:00
robert-kalmar 51a3d8ce36
Install headers to place defined by CMAKE_INSTALL_INCLUDEDIR variable (#291) 2022-02-21 10:20:38 +08:00
yingshengBD f80e1b196f
Fix compile error in g++5.4 (#286) 2022-02-11 08:20:05 +08:00
Sven 7c1a00213b
[New API] Add compile_option support - relax_mode (#285) 
Added new API for tim::vx::Context::CreateGraph with a CompileOption

Only one option added in CompileOption:
    relax_mode : Run float32 mode with bfloat16

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-09 10:52:11 +08:00
Sven 86fcb0d0e0
Fix build error with gcc 6.2.0 (#282) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-27 11:42:12 +08:00
Sven 19e4e86651
Support NPU access large memory > 4G (#280) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-26 16:00:14 +08:00
chxin66 3b11a6a5b2
Added a matmul unit_test for issue 271 (#278) 
https://github.com/VeriSilicon/TIM-VX/issues/271

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-19 22:35:44 +08:00
chxin66 32308f62c5
Add softmax unit test (#274) 
https://github.com/VeriSilicon/TIM-VX/issues/266

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-19 14:54:39 +08:00
Sven a02900d135
Fix regression introduced by V1.1.37 update (#275) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-18 11:36:09 +08:00
onepick 7fa5223943
Disable float32 to float16 conversion by default(#267) 
Disable conversion since this will impact the precision. User should enable this conversion explicitly.

Signed-off-by: Jia <juku.jia@verisilicon.com>

Co-authored-by: Jia <juku.jia@verisilicon.com>
 2022-01-14 17:18:16 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-14 12:34:38 +08:00
Antkillerfarm 36e6afa567
add alpha & beta parameters for HardSigmoid (#265) 2022-01-13 14:17:19 +08:00
Antkillerfarm 9813a5da9a
add vxc binary for internal ops (#255) 
cmake -DUSE_VXC_BINARY=1 -DVCCOMPILER_PATH=<vcCompiler path> -DGPU_CONFIG_FILE=<gpu config file> ..
 2022-01-12 11:04:49 +08:00
Zongwu.Yang 4229ad88b3
support conv3d (#238) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2022-01-11 14:13:15 +08:00
Sven ff25226adb
[Internal] support prebuilt kernel into shared library (#260) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-11 11:45:29 +08:00
Sven c1ed45150d
Added strided_slice test case with 5D-tensor (#261) 
test case can be found
    https://github.com/VeriSilicon/TIM-VX/issues/213

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 17:06:26 +08:00
Sven 58d2c0dedc
Fix GCC5 build error (#259) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-10 01:56:36 +08:00
Sven ed47c5c24c
Update internal to 1.1.37_preview (#254) 
* update internal to V1.1.37

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update VSimulator V6.4.9 for linux x86_64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 01:56:00 +08:00
liyuenan 7c63ba621e
Map OneHot & unit test (#258) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-05 22:04:49 +08:00
Goose Bomb 8e4ab68213
Fix warnings relating to inheritance (#256) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance
 2022-01-04 14:35:17 +08:00
chxin66 eecbe264b6
Add a unit_test for div_uint8 (#251) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-30 13:31:30 +08:00
liyuenan 6275f84575
Fix the conflict for previous two commits (#253) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 15:38:42 +08:00