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274 Commits

Author SHA1 Message Date
chxin66 6424ef104e
Fixed the IOtensor order difference between src_graph and infer_graph 
* Fixed the IOtensor order difference between src_graph and infer_graph

Graph Input/Output tensor sequence may changed after graph
transformation(layout infer), it is difficult to get the IO mapping
between original graph and final graph.

Clients such as the Android Support Library create tensors using the
original input/output order, which may not be the same as the input
order of src_graph, the data can not be setup correctly.

Solution:
Decide the order of inputs/outputs while creating tensor not at binding to
operation. The order of binding could be change in each transform.

Type:Code improvement

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

* Fixed maxpoolgrad maxpoolwithargmax2 cases

Some tensors created with wrong attr

Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

---------

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2023-03-21 09:21:15 +08:00
Chen Xin f0a0f1728a Added case for hardswish 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-03-06 09:37:13 +08:00
ZhangXiang 1c6041c394 Introduce CMAKE option TIM_VX_DBG_DISABLE_TENSOR_HNDL=OFF 
Enable/Disable tensorFromHandle usage

Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2023-02-09 14:31:32 +08:00
Feiyue Chen ea4ba66b94 Refine Depth2Space op 
Change default mode from CRD_mode to DCR_mode

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-02-09 13:19:57 +08:00
Chen Xin 5e7f5cecea Fixed grouped_conv2d layout infer & Added cases 
added cases for conv2d/grouped_conv2d

Type: Bug fixed

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-01-20 15:28:21 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Chen Xin 58d36ab943 Added reduce_all layoutinfer & reduce cases 
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-01-09 09:30:44 +08:00
Feiyue Chen 789d4458ff Added 4d quantized LUT unittest for embedding_lookup 
Type: New Feature | Bug Fix | Code Improvement | Documentation
Issue: bugzilla id | jira id #No more newline after this
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-01-09 09:28:45 +08:00
Feiyue Chen 06d4747b31 Fixed wrong type of hashtable_lookup unit test 
Modified datatype of copied output so that actual float16 output can be
checked  correctly

Type: Bug Fix
Issue: Bug 34696
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-01-03 15:10:25 +08:00
meseraph cc34b5f0ea mapped pool1d 2022-12-30 10:52:28 +08:00
Chen Xin aa0b474c19 Added a case for fc 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-30 10:34:21 +08:00
Chen Xin 0e211c8efd Fixed (groupd)conv2d layout infer bug 
And added a weight_as_input case to test

Type: Bug Fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:20:56 +08:00
Feiyue Chen ac4517b5c1 Added EmbeddingLookup 4d support internal 
Added EmbeddingLookup internal support for 4d lut input

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:09:19 +08:00
Feiyue Chen 06b88e7940 Fixed nn_params in groupconv2d 
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:08:14 +08:00
Feiyue Chen c6919248e1 fixed groupconv2d params in internal 
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:04:54 +08:00
Chen Xin 7582b57edc Added pad_v2 & pad_v2 layout infer 
And added 4 rank case

Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:03:58 +08:00
Feiyue Chen 8d8f4b6e68 Added EmbeddingLookup & deprecate LshProjection 
Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-05 09:59:56 +08:00
Qin.Chen 13da73bbe3 Fix maxpoolgrad, hide unused pool value output 
Type: Bug Fix
 2022-12-01 15:49:38 +08:00
Feiyue Chen b7478f7872 Added invalidate handle marco 
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 15:37:33 +08:00
Feiyue Chen f7b49ae4e2 Modified README.md about rnn&lstm 
Changed status of UnidirecitonalRnn&BidirectionalRnn
Changed status and internal op of BidirectionalLstm

Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 10:56:48 +08:00
Feiyue Chen dd7cd2504c Added HashtableLookup Op 
Added HashtableLookup Op and unit test

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 10:55:21 +08:00
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs 
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-28 09:45:50 +08:00
Feiyue Chen 05a1c561af Added layout_inference for UnidirectionalRnn 
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-23 20:58:00 +08:00
Qin.Chen 8cd5bd93ce Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now. 2022-11-22 21:39:02 +08:00
Tang d723ffaf51 fix typo for graph_test.cc 2022-11-22 21:37:40 +08:00
Chen Xin 545d677160 diabled a failed case 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-22 21:36:41 +08:00
Chen Xin 9fe7b955e5 Fixed average pool layout infer 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-16 13:34:31 +08:00
meseraph 883334e1bb add rnn 2022-11-16 13:33:39 +08:00
Feiyue Chen 11fd278d7a Fixed BidirectionalSequenceLSTM bug 
Fixed input error of  the backward direction
Fixed golden error of unit test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-16 13:31:23 +08:00
Kee 4db479ece4 Set RNN internal dtype 
Init RNN internal dtype to avoid the
internal FC OP to go to the CPU path

Type:Code Improvement

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-11-14 09:39:27 +08:00
Chen Xin 6816a0188a Added minimum unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:03:46 +08:00
Chen Xin 8867c8de35 Fixed roi_align golden mismatch error 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:02:36 +08:00
Feiyue Chen ed162d0176 Update internal for 22Q3 release 
update internal to commit-id: e2b0fde631fce349e0e3ad42b2a4d40ce7634a97

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-10-08 21:42:02 +08:00
Feiyue Chen a038df2a84 added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429 2022-10-08 14:47:07 +08:00
Chen Xin 20db77ee61 Added two cases in strided_slice 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-29 20:24:09 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00
Feiyue Chen 264e491d2a added cumsum op & added handle api after BindInput 2022-09-26 14:27:48 +08:00
Feiyue Chen 9cb37b920f added MaxPool3d op 2022-09-26 13:32:56 +08:00
Feiyue Chen 8b8d09aea3 added Rcp op & modified test_utils 2022-09-22 12:15:02 +08:00
Feiyue Chen 1b07b022e2 added sign & softsign 2022-09-20 22:49:45 +08:00
Feiyue Chen f4d5e170de added & modified copyright of some files 2022-09-20 22:47:33 +08:00
Feiyue Chen 84b464ee8b Update README.md 2022-09-20 22:47:33 +08:00
Feiyue Chen 6099022f00 added Mod op & Mod unit test 2022-09-20 22:47:33 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
Feiyue Chen 113c3722cb supported int16 dfp quantization & added conv2d unit test 2022-09-15 22:15:22 +08:00
Feiyue Chen 95401036ab fixed some errs on gcc12 2022-09-15 21:26:43 +08:00
Chen Xin 6d9ed7b25b Disabled a conv3d case 
because of some branches are not fully supported

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-15 10:46:05 +08:00
Chen Xin 0bb547b8e4 disabled two Div cases 
int32 type not supported in branch 234062
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-06 23:58:03 +08:00