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64 Commits

Author SHA1 Message Date
zhao.xia 260b0c3f2d Update Resize1d cases 
Fix resize1d uint8 bilinear case to float.
Add new uint8 resize nearest case.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 13:55:30 +08:00
Kainan Cha 2ff1f5fed1 Update operation README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 13:52:56 +08:00
Sven df77848c34
Refine unit test case name (#70) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-25 11:19:42 +08:00
Nightingale f90f3eedfd
Add map for Resize1d (#69) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 10:27:23 +08:00
Kainan Cha d0dadbc0fb Add support for FloorDiv 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 01:20:43 +08:00
Kainan Cha 804e068374 Move conv2d_test.cc to ops/ directory 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 00:39:41 +08:00
Nightingale 33fd1f0c58
Add map for DeConv1d (#62) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-24 23:41:15 +08:00
Sven 410cd8e516
Refine the cmake build (#63) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-24 13:40:37 +08:00
jing.tang 3339135c82 add docs for ops 2021-05-21 18:39:59 +08:00
Jing.Deng 3f6d697cb8 add float unit_test for conv2d 
Signed-off-by: jing.deng <Jing.Deng@verisilicon.com>
 2021-05-21 18:13:02 +08:00
zhao.xia be0a566042 Add map for Conv1D 
Convolution 1D operation, support float32, int8, int16, uint8.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-21 12:46:56 +08:00
zhao.xia 88f7141cfe Support LayerNormalization 
Layer normalization only support float32 data type.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-21 12:46:19 +08:00
Sven c3858af4fc
Fix bazel build by warning as error (#58) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 16:23:04 +08:00
zhao.xia b4b6a369a7 Add map for InstanceNormalization 
Currently instance normalization only support float32 data type.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-20 12:41:25 +08:00
Sven e3b127df50
Add group parameter for deconv API (#51) 
* Add group parameter for deconv API

Limitation: only support depthwise deconvolution

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Add single channel case and fix build warning

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 10:56:52 +08:00
Kainan Cha 7c0d2f59bb Update op README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-20 06:15:46 +08:00
xiang.zhang b1b7eadefc Add group parameter for deconv API 
Limitation: only support depthwise deconvolution

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 06:15:28 +08:00
Kainan Cha baea9b827f Add ANEURALNETWORKS API reference 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-18 14:24:17 +08:00
Kainan Cha 7770a8fd91 Update Op README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-18 02:07:52 +08:00
Kainan Cha e05b6f7404 Update operation README with reference 
These links are for reference only, actually implementation
may vary in terms of dimensions and parameters supported.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-18 01:58:08 +08:00
Sven 66dd29703e
Refine cmake build: add gtest (#47) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-17 13:04:45 +08:00
liyuenan cc3b8c1fe0
Support layout inference for FC and Resize (#45) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-15 22:42:11 +08:00
liyuenan 55ef50385e
Change back the inferface name (#44) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-14 20:08:53 +08:00
Zongwu.Yang b38cad9f1d
Add data layout for kernel to support TVM conv2d (#40) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-14 14:00:02 +08:00
liyuenan 748274143b
support layout inference for operations (#39) 
Add layout inference support for space2depth, depth2space, space2batch, batch2space, pad and
reduce.

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-13 22:27:23 +08:00
Kainan Cha d645494dcc Refine support for data copy operation 
* Properly support tensor handle for both input and output
* Fix UT to use size_in_bytes instead of size in elements

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 22:59:36 +08:00
Kainan Cha ef69e466c7 Move all UT to tim/vx/ut directory 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 16:32:40 +08:00
Kainan Cha 52401b52a5 Minor update to graph_test 
Update graph_test to demonstrate that CompileToBinary
does not require input data.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 13:31:19 +08:00
Kainan Cha 301d88a5a6 Add support for relational ops 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 23:39:22 +08:00
Kainan Cha d92e08e502 Add support for Cast and Floor operation 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 18:45:28 +08:00
Kainan Cha 2b29d5d41c Fix file permission 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 11:01:21 +08:00
Kainan Cha c2e10efb50 Add support for Reorg 
The Reorg implementation is that of YOLOv2.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 10:57:56 +08:00
Zongwu.Yang 22d423714f
Optimize permute op for constant tensor (#37) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-10 23:06:04 +08:00
Sven 5cfa7a2c40
Cmake build improvement (#36) 
Added "make install" support for cmake
Fixed symbol removed during link because no reference

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-08 23:02:04 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
Kainan Cha 31969a7326 Add support for Android make 
This change adds support for building TIM-VX under a
Android AOSP environment.

Instructions below based on Khadas VIMS system

* Add TIM-VX git repository to Android AOSP

  # cd vendor/amlogic/common/npu
  # git clone git@github.com:VeriSilicon/TIM-VX.git tim-vx

* Include tim-vx/Android.mk to AOSP build

  Edit vendor/amlogic/common/npu/Android.mak

    +TMP_PATH := $(LOCAL_PATH)
    +VIVANTE_SDK_DIR := $(LOCAL_PATH)/service/ovx_inc
    +include $(LOCAL_PATH)/tim-vx/Android.mk
    +LOCAL_PATH := $(TMP_PATH)

    ifeq ($(BOARD_NPU_SERVICE_ENABLE), true)

  Note VIVANTE_SDK_DIR needs to point to SDK header
  inclusion path

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-06 18:53:51 +08:00
Kainan Cha 88f83019a8 Use RTNE as default rounding policy 
RTNE, Round To Nearest Even is a better rounding policy
which aligns with implementation of Tensorflow Lite.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-27 15:30:15 +08:00
zhengzhouheng eff71c38bf add argmin and argmax op 2021-04-16 00:34:29 +08:00
yuenan.li c9d3416c6b Add the Squeeze op 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-04-15 11:22:48 +08:00
zhengzhouheng dc67e9ac63 add the Stack op 2021-04-07 19:57:28 +08:00
Kainan Cha 165b3fcf8f Minor clean up 
Fix typos and move functions into appropriate files

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-07 13:03:56 +08:00
zhengzhouheng 07fc3b9914 add the clip, dropout, batchnorm op 2021-04-07 13:00:41 +08:00
Kainan Cha 90a52ea6c9 Add support for Mish, SoftRelu and HardSigmoid 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-31 12:00:02 +08:00
Kainan Cha f92a5de68b Set Graph Version during in Compile() 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:11:06 +08:00
Kainan Cha c569555f1f Use FCL2 instead of FCL which supports axis 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:08:22 +08:00
Kainan Cha c141416238 Update internal to REL/v1.1.30.2 
SHA: 2e64046f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 16:25:12 +08:00
yuenan.li b5f2666e92 Map Select 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-03-25 17:27:04 +08:00
Kainan Cha 0d7afd9d51 Minor cleanup 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-19 11:12:12 +08:00
Kainan Cha cfc70c48df Use auto shape for virtual tensors 
Use auto shape for virtual tensors so that TIM-VX can
perform its internal shape inference and graph
optimizations.

Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-18 14:24:10 +08:00
Kainan Cha b6f0ffaef6 Fix Mutliply API 
Internal ops require a scale parameter to be initialized
to 1.0f.

Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-17 17:56:11 +08:00